EA-XPR-006 Embedded Artists, EA-XPR-006 Datasheet - Page 22

• Manufacturer Part Number: EA-XPR-006
• Description: BOARD LPCXPRESSO LPC11C24
• Manufacturer: Embedded Artists

Specifications of EA-XPR-006

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC11CX2_CX4
Product data sheet
7.15.1 Features
7.16.1 Crystal oscillators
7.14 System tick timer
7.15 Watchdog timer
7.16 Clocking and power control
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
The LPC11Cx2/Cx4 include three independent oscillators. These are the system
oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can
be used for more than one purpose as required in a particular application.
Following reset, the LPC11Cx2/Cx4 will operate from the Internal RC oscillator until
switched by software. This allows systems to operate without any external crystal and the
bootloader code to operate at a known frequency.
See
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– Toggle on match.
– Do nothing on match.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of Watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
Figure 5
for an overview of the LPC11Cx2/Cx4 clock generation.
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
Rev. 3 — 27 June 2011
 4.
cy(WDCLK)
 256  4) to (T
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
cy(WDCLK)
 2
© NXP B.V. 2011. All rights reserved.
24
 4) in
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