ATA557001C-DDB Atmel, ATA557001C-DDB Datasheet - Page 15

no-image

ATA557001C-DDB

Manufacturer Part Number
ATA557001C-DDB
Description
IC IDIC SENSOR RW 1KBIT DIE
Manufacturer
Atmel
Series
-r
Datasheet

Specifications of ATA557001C-DDB

Function
Read/Write
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Figure 5-1.
9191B–RFID–05/11
* p = page selector
Modulation Defeat
ATA5570C Functional Diagram
gap
Data verification failed
If the command sequence is validated and the addressed block is not write-protected, the new
data will be programmed into the EEPROM memory. The new state of the block-write protec-
tion bit (lock bit) will be programmed at the same time accordingly.
Each programming cycle consists of 4 consecutive steps.
to page 0
Reset
1. Erase block
2. Erase verification (data = “0”)
3. Programming
4. Write verification (corresponding data bits = “1”)
• If a data verification error is detected after an executed data block programming, the tag will
stop modulation (modulation defeat) until a new command is transmitted.
Page 0
single gap
OP(00)
command mode
Page 1
OP(1p)*
Command Decode
Write
Regular-read Mode
addr = 1 to maxblk
Program and Verify
Password check
Power-on Reset
Number of bits
Lock bit check
Setup Modes
OP(10..)
OP(11..)
Write
Start
Gap
AOR = 0
Page 0
gap
AOR = 1
fail
fail
fail
ok
Block-read Mode
OP(01)
addr = current
Direct access OP (1p)*
if master key <> 6
data = new
data = old
data = old
data = old
Test-mode
Page 0 or 1
OP (1p)*
Atmel ATA5570C
AOR Mode
15

Related parts for ATA557001C-DDB