SI4705-D60-EVB Silicon Laboratories Inc, SI4705-D60-EVB Datasheet - Page 7

• Manufacturer Part Number: SI4705-D60-EVB
• Description: BOARD EVALUATION FOR SI4705-D60
• Manufacturer: Silicon Laboratories Inc
• Series: -r
• Type: Receiverr

Specifications of SI4705-D60-EVB

• Frequency: 64MHz ~ 108MHz
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: SI4705

Table 4. Reset Timing Characteristics
(V
Parameter
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
A
= 2.7 to 5.5 V, V
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
4. If GPO1 and GPO2 are actively driven by the user, then minimum t
high) does not occur within 300 ns before the rising edge of RST.
after the first start condition.
rising edge of RST.
minimum t
GPO2 low.
SRST
D
= 1.62 to 3.6 V, T
is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
Figure 1. Reset Timing Parameters for Busmode Select
GPO2/
A
GPO1
= –20 to 85 °C)
RST
INT
70%
30%
70%
30%
70%
30%
1,2,3
Rev. 1.0

t
SRST
Symbol
t
t
HRST
SRST
t
HRST
SRST
is only 30 ns. If GPO1 or GPO2 is hi-Z, then
Min
100
30
Si4704/05-D60
Typ
—
—
Max
—
—
Unit
µs
ns
7