3342-7 Peregrine Semiconductor, 3342-7 Datasheet - Page 5

• Manufacturer Part Number: 3342-7
• Description: PROGRAMMING BOARD FOR PE3342
• Manufacturer: Peregrine Semiconductor
• Series: -r

Specifications of 3342-7

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 3342-07

PE3342
Product Specification
Table 7. AC Characteristics
V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
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Control Interface and Registers (see Figure 4)
EEPROM Erase/Write Programming (see Figures 5 & 6)
Main Divider (Including Prescaler)
Main Divider (Prescaler Bypassed)
Reference Divider
Phase Detector
SSB Phase Noise (F
DD
Symbol
= 3.0 V, -40° C < T
t
t
t
t
t
t
t
t
EEPW
t
P
P
DHLD
EESU
t
CWR
WRC
f
ClkH
DSU
t
t
F
F
F
P
ClkL
VPP
PW
Clk
CE
EC
f
f
FIn
FIn
In
In
In
r
c
fr
f
specification.
Rise and fall times of the V
The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14,
Ordering Information, for ordering details.
CMOS logic levels can be used to drive F
of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum
frequency limit exists when operated in this mode.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Clk
is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify f
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Data set-up time to Clock rising edge
Data hold time after Clock rising edge
S_WR pulse width
Clock rising edge to S_WR rising edge
Clock falling edge to E_WR transition
S_WR falling edge to Clock rising edge
E_WR transition to Clock rising edge
EELoad rising edge to V
V
V
Operating frequency
Operating frequency
Input level range
Operating frequency
Input level range
Operating frequency
Reference input power (Note 4)
Comparison frequency
100 Hz Offset
1 kHz Offset
PP
PP
in
pulse width
pulse rise and fall times
= 1.3 GHz, f
A
< 85° C, unless otherwise specified
r
= 10 MHz, f
PP
programming voltage pulse must be greater than 1 µs.
Parameter
PP
rising edge
c
= 1.25 MHz, LBW = 70 kHz, V
In
input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum
(Note 1)
(Note 2)
Speed-grade option (Note 3)
External AC coupling
(Note 4)
External AC coupling (Note 4)
(Note 5)
Single ended input
(Note 6)
DD
= 3.0 V, Temp = -40° C
Conditions
©2005-8 Peregrine Semiconductor Corp. All rights reserved.
)
Min
500
300
300
30
30
10
10
30
30
30
30
30
25
50
-5
-5
-2
1
Max
2700
3000
270
100
-75
-85
10
20
30
5
5
Page 5 of 17
dBc/Hz
dBc/Hz
Units
MHz
MHz
MHz
dBm
MHz
dBm
MHz
dBm
MHz
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clk