ZMOT0BSB0C0AG Zilog, ZMOT0BSB0C0AG Datasheet - Page 41

• Manufacturer Part Number: ZMOT0BSB0C0AG
• Description: Processors - Application Specialized ZMB Nic RE200B-P Pyr Fr CM 0.77 GI V5 Len
• Manufacturer: Zilog

Specifications of ZMOT0BSB0C0AG

• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Core: Z8FS040
• Number Of Timers: 2
• Processor Series: ZMOTION
• Program Memory Size: 4 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Details

PS028511-0112
Window Size (Bits 4–3)
Window Update Rate (Bits 2–0)
Bit
Field
Control
Address
PIR Process Rate (Bits 7–0)
Note: The 16-bit value provided by these two 8-bit registers must be read as an atomic operation by the application.
Controlled by the application.
This register determines the size of the control limit window. A larger window size produces more
stable control limits at the cost of additional CPU usage. If a smaller window size is used, the more
frequently the window can be calculated which allows it to track the signal better.
Controlled by the application.
This register determines how frequently the control limits are calculated. It is measured in PIR samples.
A smaller number produces more frequent calculations which allow the control limits to track the signal
better, at the cost of increased CPU usage. The valid range is 0 to 7.
• The window is updated every 4 + (Window Update Rate * 2) PIR samples.
Controlled by PIR engine
The PIR Process Rate Indicator is provided by the Engine to determine if the user application process
and interrupts overhead is impacting the performance of the Engine. If the Engine process rate drops
significantly, its ability to detect motion can be significantly reduced. This value is typically used at the
application development stage. This number gives an indication of how much CPU time the Engine is
receiving. Higher numbers are better. Generally, if the process rate drops below 0080h, the ability to
detect motion could be compromised.
This can be ensured by either using the CPU’s ATM instruction or by disabling interrupts while reading the two
8 bit registers.
00 = Reserved
01 = Small window
02 = Medium window
03 = Large window
15
14
Table 20. PIR Process Rate (ePIR_Process_Rate)
13
12
F3H
11
10
9
PIR Process Rate
8
ZMOTION™ Detection and Control Family
Read
7
6
5
4
Product Specification
F4H
Advanced API Register Set
3
2
1
0
34