M58WR032KU70ZA6U NUMONYX, M58WR032KU70ZA6U Datasheet - Page 44

• Manufacturer Part Number: M58WR032KU70ZA6U
• Description: NUMM58WR032KU70ZA6U NUM 32MB NOR FLASH P
• Manufacturer: NUMONYX

Configuration Register
8.7
8.8
8.9
8.10
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Burst Type bit (CR7)
The Burst Type bit is used to configure the sequence of addresses read as sequential or
interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses;
when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See
Burst type
each mode.
Valid Clock Edge bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during
Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of
the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock
is active.
Power-Down bit (CR5)
The Power-Down bit is used to enable or disable the Power-Down function. When it is set to
‘0’ the Power-Down function is disabled. If the Reset/Power-Down, RP, pin goes Low (V
the device is reset and the supply current I
the Power-Down bit is set to ‘1’ the Power-Down function is enabled. If the Reset/Power-
Down, RP, pin goes Low
current I
The recovery time after a Reset/Power-Down, RP, pulse is significantly longer when Power-
Down is enabled (see
Wrap Burst bit (CR3)
The burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the
boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When
the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does
not wrap.
DD
definition, for the sequence of addresses output from a given starting address in
is reduced to the Reset/Power-Down value, I
Table 28: Reset and Power-up ac
(V
IL
) the device switches to the Power-Down state and the supply
DD
is reduced to the Standby value I
DD2
characteristics).
.
M58WRxxxKU, M58WRxxxKL
DD3
Table 13:
. When
IL
),