EX256-TQG100 Actel, EX256-TQG100 Datasheet - Page 25

• Manufacturer Part Number: EX256-TQG100
• Manufacturer: Actel

eX Family Timing Characteristics
Table 1-17 • eX Family Timing Characteristics
Parameter
C-Cell Propagation Delays
t
Predicted Routing Delays
t
t
t
t
t
t
t
t
R-Cell Timing
t
t
t
t
t
t
t
t
2.5 V Input Module Propagation Delays
t
t
3.3 V Input Module Propagation Delays
t
t
Input Module Predicted Routing Delays
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
PD
DC
FC
RD1
RD2
RD3
RD4
RD8
RD12
RCO
CLR
PRESET
SUD
HD
WASYN
RECASYN
HASYN
INYH
INYL
INYH
INYL
IRD1
IRD2
IRD3
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
(Worst-Case Automotive Conditions, V
Description
Internal Array Module
FO=1 Routing Delay, DirectConnect
FO=1 Routing Delay, FastConnect
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
Sequential Clock-to-Q
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Hold Time
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
2
1
PD
+ t
RD1
+ t
PDn
2
, t
RCO
CCA
+ t
RD1
= 2.3 V, T
+ t
v3.2
PDn
or t
J
= 125°C)
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
Min.
0.8
0.0
2.2
0.6
0.6
‘Std.’ Speed
eX Automotive Family FPGAs
Max.
1.1
0.1
0.6
0.6
0.7
0.9
1.1
1.9
2.8
1.0
0.9
1.0
1.1
1.4
1.3
1.6
0.5
0.7
0.9
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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