EX256-FCS100 ETC1 [List of Unclassifed Manufacturers], EX256-FCS100 Datasheet

EX256-FCS100

Manufacturer Part Number

EX256-FCS100

Description

eX Family FPGAs

Manufacturer

ETC1 [List of Unclassifed Manufacturers]

Datasheet

1.EX256-FCS100.pdf (36 pages)

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eX Family FPGAs

Le a di n g E d ge P er f o r m a n ce

• 240 MHz System Performance

• 3.9ns Clock-to-Out (Pad-to-Pad)

• 350 MHz Internal Performance

Sp e ci f i c a t i on s

• 3,000 to 12,000 Available System Gates

• As Many as 512 Maximum Flip-Flops (Using CC Macros)

• 0.22 µ CMOS Process Technology

• Up to 132 User-Programmable I/O Pins

Fe a t ur es

• High-Performance, Low-Power Antifuse FPGA

• LP/Sleep Mode for Additional Power Savings

• Advanced Small-footprint Packages

• Hot-Swap Compliant I/Os

• Single-Chip Solution

• Nonvolatile

• Live on power up

• Power-Up/Down Friendly (No Sequencing Required for

• Configurable Weak-Resistor Pull-Up or Pull-Down for

eX P r o du ct Pr o f i l e

D e ce m b e r 2 0 0 1

Device

Capacity

Combinatorial Cells

Maximum User I/Os

Speed Grades

Temperature Grades

Package (by pin count)

Supply Voltages)

Tristated Outputs during Power Up

System Gates

Typical Gates

TQFP

CSP

–F, Std, –P

64, 100

49, 128

3,000

2,000

eX64

128

C, I

• Individual Output Slew Rate Control

• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V

• Software Design Support with Actel Designer Series and

• Up to 100% Resource Utilization with 100% Pin Locking

• Deterministic Timing

• Unique In-System Diagnostic and Verification Capability

• Boundary Scan Testing in Compliance with IEEE Standard

• Secure Programming Technology Prevents Reverse

G en er al D e sc r i p t i on

The eX family of FPGAs is a low-cost solution for low-power,

high-performance designs. The inherent low power

attributes of the antifuse technology, coupled with an

additional low static power mode, make these devices ideal

for power-sensitive applications. Fabricated with an

advanced 0.22 µ CMOS antifuse technology, these devices

achieve high performance with no power penalty

Input Tolerance and 5.0V Drive Strength

Libero Tools

with Silicon Explorer II

1149.1 (JTAG)

Engineering and Design Theft

–F, Std, –P

64, 100

49, 128

eX128

6,000

4,000

128

256

100

C, I

–F, Std, –P

128, 180

12,000

eX256

8,000

256

512

132

100

C, I

v 3 . 0

Related parts for EX256-FCS100

EX256-FCS100 Summary of contents

Page 1

... Std, –P –F, Std, – 64, 100 64, 100 49, 128 49, 128 eX256 12,000 8,000 256 512 132 –F, Std, – 100 128, 180 1 ...

... Speed Grade Blank = Standard Speed Part Number eX64 = eX128 = eX256 = eX64 Device 64-Pin Thin Quad Flat Pack (TQFP) 100-Pin Thin Quad Flat Pack (TQFP) 49-Pin Chip Scale Package (CSP) 128-Pin Chip Scale Package (CSP) eX128 Device ...

Page 3

The eX family architecture uses a “sea-of-modules” structure where the entire floor of ...

Page 4

Rou ti ng Res our ces Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure architecture ...

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ock Res our ce s Actel’s high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select ...

Page 6

... Product Low Power Standby Current eX64 100 eX128 111 eX256 134 Bou ndar y S can ( All eX devices are IEEE 1149.1 compliant. eX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins 6 in conjunction with the program fuse ...

Page 7

machine reaches the “logic reset” state. At this point the BST pins will be released and will function as regular I/O pins. The “logic reset” state is reached five ...

Page 8

... Devices should not be operated outside the Recommended Operating Conditions. T ypi cal andb y Cur r ent at 25° C Product eX64 eX128 eX256 2 ect r ical S pe cif i cat io ns Symbol Parameter V = MIN ...

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3 ect r ica cif i cat io ns Symbol Parameter V = MIN ...

Page 10

... D yna ower C ons – Low Fr eq uency Notes: 1. Device filled with 16-bit counters 2.7V, device tested at room temperature. CCA CCI 10 50 100 150 Frequency (MHz Frequency (MHz) v3 eX64 eX128 eX256 200 eX64 eX128 eX256 50 ...

Page 11

ota l Dy nam ic P owe 180 160 140 120 100 ...

Page 12

The temperature variable in the Designer Series software refers to the junction temperature, not the ambient temperature. This is an important distinction because ...

Page 13

Input Delays I/O Module t = 0.7 ns INYH Routed t = 1.3 ns RCKH Clock (100% ...

Page 14

GND 50% 50 1.5V Out 1. DLH DHL ...

Page 15

ip- Flo SUD CLK ...

Page 16

cia l Cond it ion s, ...

Page 17

...

Page 18

cia l Cond it ion s ...

Page 19

(Worst-Case Commercial Conditions V Parameter Description ...

Page 20

CLKA/B Clock A and B These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL or LVTTL specifications. The clock input is buffered prior ...

Page 21

64 ew 64-Pin ...

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eX64 Pin Number Function GND 1 TDI, I I/O 4 TMS 5 GND V 6 CCI I TRST ...

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...

Page 24

... I I/O 83 PRB, I CCA GND CLKA I/O 88 CLKB HCLK I/O 91 GND I/O 92 PRA, I/O I CCI I/O 95 I/O 96 I/O 97 I/O 98 TDO, I/O 99 I/O 100 TCK, I/O v3 eX128 eX256 Function Function GND GND NC I/O NC I/O NC I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I ...

Page 25

49 Ball ...

Page 26

128 Vie w) A1 Ball Pad Corner ...

Page 27

... GND GND F10 NC I/O F11 I/O F12 TDI, I I/O G2 TRST, I/O I/O G3 I/O G4 GND CLKA G9 GND I/O G10 NC I/O G11 I/O G12 NC I/O H1 GND I I/O H4 GND I/O H9 I/O H10 V v3.0 eX128 eX256 Function Function I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I CCI CCI CCI I/O I CCI CCI CCI I/O I/O I/O GND GND GND GND I/O I/O I/O 1 ...

Page 28

... L1 1 VSV L2 I CCI I/O L5 I/O L6 I/O L7 GND L8 I/O L9 GND L10 I/O L11 I/O L12 I/O M1 I/O M2 I/O M3 I/O M4 I/O M5 I/O M6 PRB, I/O M7 HCLK M8 I/O M9 I/O M10 I/O M11 TDO, I/O M12 v3 eX64 eX128 eX256 Function Function Function I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I CCI CCI CCI GND GND GND I/O I/O I/O I/O ...

Page 29

180 ew) A1 Ball Pad ...

Page 30

... K14 1 GND/ CCA I CCA I/O L5 I/O L6 I/O L7 I/O L8 GND L9 I/O L10 I/O L11 I/O L12 V L13 CCA I/O L14 I/O M1 TRST, I/O M2 I eX256 eX256 Function Pin Number Function GND M4 I/O GND M5 I/O I/O M6 I/O I/O M7 I/O I/O M8 I/O I/O M9 I/O I/O M10 I/O GND M11 I/O I/O M12 I/O V M13 V CCI CCI GND M14 I/O I/O N1 I/O ...

Page 31

... A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256 pin functions have been added. A CS180 pin drawing and pin assignment table for eX256 pin functions have been added. The following table note was added to the eX Timing Characteristics table for Advanced v ...

Page 32

order to provide the latest information to designers, some data sheets are published before data has been fully characterized. Product Briefs are modified versions ...

Page 33

v3.0 33 ...

Page 34

...

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v3.0 35 ...

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Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Europe Ltd. Maxfli Court, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 ...

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