ADXRS453BRGZ-RL Analog Devices Inc, ADXRS453BRGZ-RL Datasheet - Page 17

• Manufacturer Part Number: ADXRS453BRGZ-RL
• Manufacturer: Analog Devices Inc

Specifications of ADXRS453BRGZ-RL

• Lead Free Status / Rohs Status: Compliant

COMMAND/RESPONSE BIT DEFINITIONS
Table 12. SPI Interface Bit Definitions
Bits
SQ2 to SQ0
SM2 to SM0
A8 to A0
D15 to D0
P
SPI
RE
DU
ST1, ST0
P0
P1
SQ2 to SQ0 Bits
The SQ2 to SQ0 bits provide the system with a means of synchro-
nizing the data samples that are received from multiple sensors.
To facilitate correct synchronization, the ADXRS453 gyroscope
includes the SQ[2:0] bits in the response sequence as they were
received in the request.
SM2 to SM0 Bits
The SM2 to SM0 bits are the sensor module bits from the master
device. These bits are not implemented in the ADXRS453 and
are hard-coded to 000 for all occurrences.
A8 to A0 Bits
The A8 to A0 bits represent the memory address for data read or
data write. These bits should be supplied by the master when the
memory registers are being accessed; these bits are ignored for all
sensor data requests. For a complete description of the available
memory registers, see the Memory Register Definitions section.
D15 to D0 Bits
The D15 to D0 bits are the 16-bit device data, which can
contain any of the following:
•
•
•
•
P Bit
A parity bit (P) is required for all master-to-slave data transmis-
sions. The communication protocol requires one parity bit to
achieve odd parity for the entire 32-bit command. “Don’t care”
bits are also factored into the parity calculation.
Data from the master to be written to a memory register, as
specified by the A8 to A0 bits.
Sensor rate output data from the slave.
Device data from the slave read from the memory register
specified by the A8 to A0 bits, as well as the data from the
next sequential register.
Following a write command, the 16-bit data that is written
to the specified memory register in the ADXRS453 and is
reflected back to the master device for correlation.
Description
Sequence bits (from master)
Sensor module bits (from master)
Register address
Data
Command odd parity
SPI command/response
Request error
Data unavailable
Status bits
Response, odd parity, Bits[31:16]
Response, odd parity, Bits[31:0]
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SPI Bit
The SPI bit is set when either of the following occurs:
•
•
A SPI error causes the device to issue a R/W error response
regardless of the SPI command type issued by the master
device (see Table 10). In addition, any error during a sensor
data request results in the device issuing a read/write error.
RE Bit
The request error (RE) bit is the communication error bit trans-
mitted from the ADXRS453 device to the control module. Request
errors can occur when
•
•
•
DU Bit
After the chip select pin is deasserted ( CS goes high), the user
must wait 0.1 µs before reasserting the CS pin to initiate another
command/response frame with the device. Failure to adhere to
this timing specification may result in a data unavailable (DU)
error.
ST1 and ST0 Bits
The status bits (ST1 and ST0) are used to signal to the master
device the type of data contained in the response message (see
Table 13).
Table 13. Status Bit Code Definitions
ST[1:0]
00
01
10
11
Either of the following conditions can result in the ST[1:0] bits
being set to 00 during a sensor data response:
•
•
P0 Bit
P0 is the parity bit that establishes odd parity for Bits[31:16]
of the device response.
P1 Bit
P1 is the parity bit that establishes odd parity for the entire
32-bit device response.
Too many or not enough bits were transmitted.
A message from the control module contains a parity error.
An invalid command is sent from the control module.
A read/write command specifies an invalid memory
register.
A write command attempted to write to a nonwritable
memory register.
The self-test response is sufficiently different from its
nominal value (see the Specifications section for the
appropriate limits).
The PLL fault bit is active (see the PLL Bit section).
Contents of Bits[D15:D0]
Invalid data for sensor data response
Valid sensor data
Sensor self-test data
Read/write response
ADXRS453