ADC10DL065EVAL National Semiconductor, ADC10DL065EVAL Datasheet - Page 3

• Manufacturer Part Number: ADC10DL065EVAL
• Manufacturer: National Semiconductor

Specifications of ADC10DL065EVAL

• Lead Free Status / Rohs Status: Not Compliant

ANALOG I/O
DIGITAL I/O
Pin Descriptions and Equivalent Circuits
Pin No.
15
16
21
13
14
12
60
22
41
2
1
7
5
4
6
DF/DCS
Symbol
V
V
V
V
V
V
V
V
V
V
V
OEA
OEB
CLK
IN
IN
IN
IN
RM
RM
RP
RP
RN
RN
REF
A+
B+
A−
B−
A
B
A
B
A
B
Equivalent Circuit
3
Differential analog input pins. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 V
input pin voltage centered on a common mode voltage, V
The negative input pins may be connected to V
single-ended operation, but a differential input signal is
required for best performance.
This pin is the reference select pin and the external reference
input.
If (V
selected.
If AGND
is selected.
If a voltage in the range of 0.8V to 1.2V is applied to this pin,
that voltage is used as the reference. V
bypassed to AGND with a 0.1 µF capacitor when an external
reference is used.
This is a four-state pin.
DF/DCS = V
cycle stabilization applied to the input clock
DF/DCS = AGND, output data format is 2’s complement, with
duty cycle stabilization applied to the input clock.
DF/DCS = V
without duty cycle stabilization applied to the input clock
DF/DCS = "float", output data is offset binary without duty cycle
stabilization applied to the input clock.
These pins are high impedance reference bypass pins. All
these pins should each be bypassed to ground with a 0.1 µF
capacitor. A 10 µF capacitor should be placed between the
V
V
temperature stable 1.5V reference. The remaining pins should
not be loaded.
Digital clock input. The range of frequencies for this input is as
specified in the electrical tables with guaranteed performance
at 65 MHz. The input is sampled on the rising edge.
OEA and OEB are the output enable pins that, when low, holds
their respective data output pins in the active state. When
either of these pins is high, the corresponding outputs are in a
high impedance state.
RP
RM
A and V
A
A and V
- 0.3V)
<
V
RN
RM
A
RM
REF
, output data format is offset binary with duty
<
A pins and between the V
B may be loaded to 1mA for use as a
A or V
V
<
REF
(AGND + 0.3V), the internal 0.5V reference
RM
<
V
B , output data is 2’s complement
Description
A
, the internal 1.0V reference is
REF
RP
B and V
should be
P-P
CM
with each
www.national.com
for
RN
B pins.
CM
.