NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet - Page 14

• Manufacturer Part Number: NOIL1SM0300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM0300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Res2_enable (1bit)
device.
RES2_TIMER register)
- default
Res3_enable (1bit)
device.
RES3_TIMER register)
- default
Reverse_X (1bit)
bit through the SPI.
Reverse_Y (1bit)
bit through the SPI.
Ndr (1 bit)
desired.
Start_X Register <7:0>
direction. In this direction, there are 80 (from 0 to 79)
possible start positions (8 pixels are addressed at the same
time in one clock cycle). Remember that if you put Start_X
to 0, pixel 0 is being read out. Example:
from pixel 184 (8x23).
Start_Y Register <8:0>
direction. In this direction, there are 480 (from 0 to 479)
possible start positions. This means that the start position in
Y direction can be set on a line by line basis.
Nb_pix <7:0>
number of pixels to be read out is expressed as a number of
kernels in this register (4 pixels per kernel). This means that
there are 160 possible values for the register (from 1 to 160).
Example:
read out.
This bit enables/disables the dual slope mode of the
1: Dual slope is enabled (configured according to the
0: Dual slope is disabled (RES2_timer register is ignored)
This bit enables/disables the triple slope mode of the
1: triple slope is enabled (configured according to the
0: triple slope is disabled (RES3_timer register is ignored)
The readout direction in X can be reversed by setting this
1: Read direction is reversed (from right to left)
0: normal read direction (from left to right) - default
The readout direction in Y can be reversed by setting this
1: Read direction is reversed (from bottom to top)
0: normal read direction (from top to bottom) - default
This bit enables the non destructive readout mode if
1: ndr enables
0: ndr disables (default)
This register sets the start position of the readout in X
If you set 23 in the Start_X register readout only starts
This register sets the start position of the readout in Y
This register sets the number of pixels to read out. The
If you set 37 in the nb_pix register, 148 (37 x 4) pixels are
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Res1_length <11:0>
it remains high). This length is expressed as a number of
lines (res1_length - 1). The minimum and default value of
this register is 2.
following formula:
period)
Res2_timer <11:0>
pulse to enable the dual slope capability. This is also defined
as a number of lines-1.
calculated with the following formula:
period)
Res3_timer <11:0>
pulse to enable the triple slope capability. This is also
defined as a number of lines - 1.
calculated with the following formula:
period)
Ft_timer <11:0>
storage node in the pixel. This means that it also defines the
end of the integration time. It is also expressed as a the
number of lines - 1.
calculated with the following formula:
Vcal <7:0>
generates the Vcal supply used by the PGA.
When the register is 11111111 then it sets a Vcal of 0V. This
means that the minimum step you can take with the Vcal
register is 9.8 mV/bit (2.5V/256bits).
Vblack <7:0>
generates the Vblack supply used by the PGA. When the
register is ”00000000” it sets a Vblack of 2.5V. When the
register is 11111111 then it sets a Vblack of 0V. This means
that the minimum step you can take with the Vblack register
is 9.8 mV/bit (2.5V/256bits).
This register sets the length of the reset pulse (how long
The actual time the reset is high is calculated with the
Reset high = (Res1_length-1) * (ROT + Nr. Pixels * clock
This register defines the position of the additional reset
The actual time on which the additional reset is given is
DS high = (Res2_timer-1) * (ROT + Nr. Pixels * clock
This register defines the position of the additional reset
The actual time on which the additional reset is given is
TS high = (Res3_timer-1) * (ROT + Nr. Pixels * clock
This register sets the position of the frame transfer to the
The actual time on which the frame transfer takes place is
FT time = (ft_timer-1) * (ROT + Nr. Pixels * clock period)
This register is the input for the on-chip DAC which
When the register is ”00000000” it sets a Vcal of 2.5V.
This register is the input for the on-chip DAC which