NOIL1SC4000A-GDC ON Semiconductor, NOIL1SC4000A-GDC Datasheet - Page 11

• Manufacturer Part Number: NOIL1SC4000A-GDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SC4000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

supplies; for correct polarities of the signals see Table 4. The
signals in Figure 11 are generated from the on-chip drivers.
These on-chip drivers need two types of signals to generate
the exact type of signal. It needs digital control signals
between 0 V and 3.3 V (internally converted to 2.5 V) with
normal driving capability and power supplies. The control
signals are required to indicate when they must occur and the
power supplies indicate the level.
Vmem_h and Vmem_l. If the signal Mem_hl is the logic ‘0’
lower reset level during integration. This is done by the
control signal Reset_ds and by the power supply Vres_ds
that defines the level to which the pixel must be reset.
that the high voltage level is applied for reset, if both pulses
occur at the same time.
pulses with a lower Vres_ds level for each pulse given within
the same integration time.
not very fast (200 ns). In fact they are made rather slow to
limit the maximum current through the power supply lines
(Vmem_h, Vmem_l, Vres, Vres_ds, Vdd). Current
limitation of those power supplies is not required. However,
limit the currents to not higher than 400 mA.
current because it must be able to discharge the internal
capacitance from the level Vmem_h to the level Vmem_l.
The external control signals should be capable of driving
input capacitance of about 10 pF.
Table 4. OVERVIEW OF INTERNAL AND EXTERNAL PIXEL ARRAY SIGNALS
Precharge
Sample
Reset
Vmem
Internal Signal
In Figure 11, levels are defined by the pixel array voltage
Vmem is made of a control signal Mem_hl and 2 supplies
For dual slope operation, give a second reset pulse to a
Note that Reset is dominant over Reset_ds, which means
Multiple slopes are possible having multiple Reset_ds
The rise and fall times of the internal generated signals are
The power supply Vmem_l must be able to sink this
2.0 V to 2.5 V
Vlow
0
0
0
2.5 V to 3.3 V
2.5 V to 3.3 V
0.45 V
Vhigh
2.5 V
Figure 11. Internal Timing of Pixel
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Reset (AH) and Reset_ds (AH)
External Control Signal
Precharge (AL)
11
Mem_hl (AL)
Sample (AL)
than the internal signal Vmem is low, if Mem_hl is logic ‘1’
the internal signal Vmem is high.
Reset_ds, and two supplies, Vres and Vres_ds. Depending
on the signal that becomes active, the corresponding supply
level is applied to the pixel.
external pixel array signals.
Digital Signals
These signals are:
•
•
•
•
•
•
Reset is made with two control signals, Reset and
Table 4 summarizes the relation between the internal and
The digital signals control the readout of the image sensor.
Sync_y (AH
pulse synchronises the y-address register: active high.
This signal is also the end of the frame or window and
determines the window width.
Clock_y (AH
edge of this clock, the next line is selected.
Sync_x (AH
at the address defined by the x-address register. This
pulse synchronises the x-address register: active high.
This signal is also the end of the line and determines the
window length.
Clock_x (AH
33 MHz is required to achieve a pixel rate of 66 MHz.
Spi_data (AH
Spi_clock (AH
downloads the data into the SPI register.
[10]
[10]
[10]
[10]
[10]
[10]
): Starts the readout of the frame. This
): Starts the readout of the selected line
): Clock of the y-register. On the rising
): Determines the pixel rate. A clock of
): Data for the SPI.
Low DC Level
): Clock of the SPI. This clock
Vmem_l
Vpre_l
Gnd
Gnd
Controlled by
bias-resistor
Vdd
Vres and Vres_ds
Vmem_h
High DC Level