NOIL1SM4000A-GDC ON Semiconductor, NOIL1SM4000A-GDC Datasheet - Page 17

• Manufacturer Part Number: NOIL1SM4000A-GDC
• Description: LUPA4000 MONO PGA127
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM4000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

and output. Output level before the first pixel is the level of
the last pixel on previous line.
occurs, the pixels are brought to the analog outputs. This is
again the simulation result of a comparable sensor to show
the principle.
moment the data is seen at the output. Because it is difficult
to predict this time difference in advance, have the ADC
sampling clock flexible to set an optimal ‘add sampling’
point. The time differences can easily vary between 5 ns and
15 ns and must be tested on the real devices.
made active for about 20 ns from the moment the next line
is selected. The time these pulses must be active is related to
the biasing resistance Pre_load. The lower this resistance,
In the figure, shown from bottom to top: Clock_x, Sync_x
As soon as Sync_x is high and one rising edge of Clock_x
Note the time difference between the clock edge and the
In this case, the control signals Norowsel and pre_col are
Figure 19. Standard Timing for ROT (only pre_col and No_row_sel control signals are required)
Figure 18. Output Signal Related to Clock_x Signal
dark
P
ixel 1
http://onsemi.com
Pixel 20.: Pixel period : 20 nsec
17
Reduced ROT Timing
you must wait to get the data stable at the column amplifiers.
It is a loss in time, which should be reduced as much as
possible.
Standard Timing (200 ns)
made active for about 20 ns from the moment the next line
is selected. The time these pulses must be active is related to
the biasing resistance Pre_load. The lower this resistance,
the shorter the pulse duration of Norowsel and pre_col may
be. After these pulses are given, wait for at least 180 ns
before the first pixel is sampled. For this mode, Sh_col must
always be active (low).
the shorter the pulse duration of Norowsel and pre_col may
be. After these pulses are given, wait for at least 180 ns
before the first pixel is sampled. For this mode Sh_col must
be made active (low) all the time.
The ROT is the time between the selection of lines that
In this case, the control signals Norowsel and pre_col are
s
aturated
Clock_x:
25MHz
Output 1
Sync_x