74LVC4066PW,112 NXP Semiconductors, 74LVC4066PW,112 Datasheet - Page 10

IC SWITCH QUAD SPST 14TSSOP

74LVC4066PW,112

Manufacturer Part Number
74LVC4066PW,112
Description
IC SWITCH QUAD SPST 14TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC4066PW,112

Package / Case
14-TSSOP (0.173", 4.40mm Width)
Function
Switch
Circuit
4 x SPST - NO
On-state Resistance
6 Ohm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
1.65 V ~ 5.5 V
Current - Supply
0.1µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Switch Configuration
SPST
On Resistance (max)
34 Ohm (Typ) @ 1.95 V
On Time (max)
5.3 ns (Typ) @ 1.95 V
Off Time (max)
4.2 ns (Typ) @ 1.95 V
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3021-5
935273718112
NXP Semiconductors
10. Dynamic characteristics
Table 8.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit
[1]
[2]
[3]
[4]
[5]
[6]
74LVC4066
Product data sheet
Symbol Parameter
t
t
t
C
pd
en
dis
PD
Typical values are measured at T
t
Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
t
t
C
P
f
f
C
C
V
N = number of inputs switching;
{(C
pd
en
dis
i
o
D
CC
PD
= input frequency in MHz;
L
S(ON)
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
+ C
propagation delay nY to nZ or nZ to nY;
enable time
disable time
power dissipation
capacitance
PD
= maximum ON-state switch capacitance in pF;
Dynamic characteristics
S(ON)
 V
CC
)  V
2
 f
PLH
PZH
PLZ
CC
i
 N + {(C
2
and t
and t
and t
 f
o
} = sum of the outputs.
PHL
PZL
PHZ
Conditions
see
nE to nY or nZ; see
nE to nY or nZ; see
C
V
I
.
L
.
.
L
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= GND to V
+ C
= 50 pF; f
amb
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
Figure 15
S(ON)
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 2.5 V
= 3.3 V
= 5.0 V
= 25 C and nominal V
)  V
All information provided in this document is subject to legal disclaimers.
i
= 10 MHz;
CC
CC
2
Rev. 4 — 24 November 2010
 f
Figure 16
Figure 16
o
} where:
D
CC
in W).
.
[2][3]
[4]
[5]
[6]
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
-
-
-
-
-
-
-
-
40 C to +85 C
Typ
12.5
15.6
11.0
0.8
0.4
0.4
0.3
0.2
5.3
3.0
2.6
2.5
1.9
4.2
2.4
3.6
3.4
2.5
[1]
Max
2.0
1.2
1.0
0.8
0.6
5.6
5.0
4.4
3.9
9.0
5.5
6.5
6.0
5.0
10
-
-
-
74LVC4066
40 C to +125 C Unit
Quad bilateral switch
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
-
-
-
-
-
-
-
-
Figure
© NXP B.V. 2010. All rights reserved.
17.
Max
12.5
11.5
3.0
2.0
1.5
1.5
1.0
7.0
6.5
5.5
5.0
7.0
8.5
7.5
6.5
-
-
-
10 of 23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF

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