M25P64-VME6TG Micron Technology Inc, M25P64-VME6TG Datasheet
M25P64-VME6TG
Specifications of M25P64-VME6TG
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M25P64-VME6TG Summary of contents
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... More than 100 000 Erase/Program cycles per sector More than 20-year data retention Packages – RoHS compliant Automotive certified parts available May 2009 64 Mbit, low voltage, Serial Flash memory with 75 MHz SPI bus interface = Rev 9 M25P64 VDFPN8 (ME) 8 × (MLP8) SO16 (MF) 300 mils width 1/54 www.numonyx.com 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M25P64 Mbit ( Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus instructions allowing clock frequency MHz. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. An enhanced Fast Program/Erase mode is available to speed up operations in factory environment ...
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... CC V Ground SS Figure 2. VDFPN connections 1. There is an exposed central pad on the underside of the VDFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Section 11: Package mechanical M25P64 V SS AI07485B Function M25P64 HOLD W ...
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... Figure 3. SO connections Don’t Use 2. See Section 11: Package mechanical 8/54 M25P64 HOLD W/V PP AI07486C for package dimensions, and how to identify pin-1. ...
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Signal description 2.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data Input (D) This input ...
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Write Protect/Enhanced Program supply voltage (W/V W/V is both a control input and a power supply pin. The two functions are selected by the PP voltage range applied to the pin. If the W/V input is kept in a ...
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... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P64 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at ...
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Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 μs. Figure 5. SPI modes supported CPOL CPHA ...
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Operating features 4.1 Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the ...
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Active Power and Standby Power modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P64 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertant changes while the power supply is outside the operating specification. ...
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Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is ...
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Memory organization The memory is organized as: 8388608 bytes (8 bits each) 128 sectors (512 Kbits, 65536 bytes each) 32768 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device ...
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Table 3. Memory organization Sector 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 ...
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Table 3. Memory organization (continued) Sector ...
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Table 3. Memory organization (continued) Sector ...
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Table 3. Memory organization (continued) Sector Address range 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h ...
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Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven ...
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Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) ...
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Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...
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Read Identification (RDID) The read identification (RDID) instruction allows to read the device identification data: Manufacturer identification (1 byte) Device identification (2 bytes) A unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer ...
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Figure 10. Read Identification (RDID) instruction sequence and data-out sequence 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a ...
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Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in protected against Page Program (PP) and Sector Erase (SE) instructions. The ...
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Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...
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When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by ...
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Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising ...
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Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) ...
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Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the ...
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Figure 15. Page Program (PP) instruction sequence Instruction Data Byte ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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... Figure 18. Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P64, is 16h. 36/54 Figure 18 Dummy Bytes ...
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Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...
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Figure 19. Power-up timing (max (min) Reset State of the Device V WI Table 8. Power-Up timing and VWI threshold Symbol ( (min low VSL CC (1) t Time delay ...
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Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Figure 20. AC measurement I/O waveform Input Levels 0.8V CC 0.2V CC Table 13. Capacitance Symbol Parameter C Output Capacitance (Q) OUT C Input Capacitance (other pins Sampled only, not 100% tested Table 14. DC characteristics ...
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Table 15. DC characteristics process technology T9HX Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating ...
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Table 16. AC characteristics Test conditions specified in Symbol Alt. Clock Frequency for the following instructions: FAST_READ PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR f Clock Frequency for READ instructions R ( ...
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Table 17. AC characteristics, T9HX parts (page Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, SE, BE, WREN, WRDI, RDID RDSR, WRSR Clock frequency for read ...
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Table 17. AC characteristics, T9HX parts (page Test conditions specified in Symbol Alt. t Sector erase cycle time SE t Bulk erase cycle time BE 1. Technology T9HX devices are identified by process identification digit "4" in ...
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Figure 22. Write Protect setup and hold timing during WRSR when SRWD = 1 W/V PP tWHSL High Impedance Q Figure 23. Hold timing HOLD 46/54 tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439b ...
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Figure 24. Output timing S C tCLQV tCLQX tCLQX Q ADDR D LSB IN Figure 25. V timing PPH PP, SE PPH W/V PP tVPPHSL tCH tCLQV tCL tQLQH tQHQL End of PP ...
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Package mechanical Figure 26. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 × 6 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package ...
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Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width SO-H 1. Drawing is not to scale. Table 19. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width, ...
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... Reliability Certified Flow (HRCF) is described in the quality note NNEE9801. Please ask your nearest Numonyx sales office for a copy. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 50/54 M25P64 – (1) ...
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The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 51/54 ...
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Revision history Table 21. Document revision history Date Revision 28-Apr-2003 0.1 15-May-2003 0.2 20-Jun-2003 0.3 18-Jul-2003 0.4 02-Sep-2003 0.5 19-Sep-2003 0.6 17-Dec-2003 0.7 15-Nov-2004 1.0 24-Feb-2005 2.0 23-Dec-2005 3.0 16-Feb-2006 4.0 07-Sep-2006 19-Jan-2007 52/54 Target Specification Document written in ...
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Table 21. Document revision history Date Revision 10-Dec-2007 7 Applied Numonyx branding. To provide support for the Automotive market, added the following: – Automotive bullet to cover page; 30-Oct-2008 8 – Grade 3 and grade 6 information to – Table ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...