NOII4SM6600A-QDC ON Semiconductor, NOII4SM6600A-QDC Datasheet

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NOII4SM6600A-QDC

Manufacturer Part Number
NOII4SM6600A-QDC
Description
Manufacturer
ON Semiconductor
Datasheet

Specifications of NOII4SM6600A-QDC

Lead Free Status / Rohs Status
Supplier Unconfirmed
Features
Applications
Ordering Information
Note For more information, see
page 29.
©
May, 2011 - Rev. 9
Marketing Part Number
Semiconductor Components Industries, LLC, 2011
2210 (H) x 3002 (V) Active Pixels
3.5 µm × 3.5 µm Square Pixels
1 inch Optical Format
Monochrome Output
Frame Rate:
High Dynamic Range Modes: Double Slope, Non Destructive
Read out (NDR)
Electronic Rolling Shutter
Master Clock: 40 MHz
Single 2.5V supply
3.3V supply for extended dynamic range
-30°C to +65°C Operational Temperature Range
68-Pin LCC Package
Power Dissipation: 225 mW
Machine Vision
Biometry
Document Scanning
NOII4SM6600A-QDC
5 fps for active window of 2210 x 3002)
89 fps for active window of 640 x 480)
Mono with Glass
Description
Ordering Code Definition
68 pin LCC
Package
6.6 Megapixel CMOS Image Sensor
on
1
Description
The IBIS4-6600 is a solid-state CMOS image sensor that
integrates complete analog image acquisition, and a digitizer
and digital signal processing system on a single chip. This image
sensor has a resolution of 6.6 MPixel with 2210 x 3002 active
pixels. The image size is fully programmable for user-defined
windows. The pixels are on a 3.5 µm pitch.
The user programmable row and column start and stop positions
enable windowing down to 2x1 pixel window for digital zoom.
Subsampling reduces resolution while maintaining the constant
field of view. The analog video output of the pixel array is
processed by an on-chip analog signal pipeline. Double
Sampling (DS) eliminates the fixed pattern noise.
The programmable gain and offset amplifier maps the signal
swing to the ADC input range. A 10-bit ADC converts the analog
data to a 10-bit digital word stream. The sensor uses a three-wire
Serial-Parallel (SPI) interface. It operates with a single 2.5V
power supply and requires only one master clock for operation
up to 40 MHz. It is housed in a 68-pin ceramic LCC package.
This data sheet enables the development of a camera system,
based on the described timing and interfacing given in the
following sections.
Figure 1. IBIS4-6600 Image Sensor
NOII4SM6600A
Publication Order Number:
NOII4SM6600A/D

Related parts for NOII4SM6600A-QDC

NOII4SM6600A-QDC Summary of contents

Page 1

... Machine Vision ■ Biometry ■ Document Scanning ■ Ordering Information Marketing Part Number Description NOII4SM6600A-QDC Mono with Glass Note For more information, see Ordering Code Definition page 29. Semiconductor Components Industries, LLC, 2011 © May, 2011 - Rev. 9 6.6 Megapixel CMOS Image Sensor ...

Page 2

... Basic Line and Frame Timing ......................................23 Pixel Output Timing .....................................................24 ADC Timing .................................................................25 Package Information ........................................................26 Pin List .........................................................................26 Package Outline Drawing ............................................28 Glass Lid .....................................................................29 Handling Precautions .......................................................29 Limited Warranty ..............................................................29 Return Material Authorization (RMA) ..........................29 Acceptance Criteria Specification ...................................29 Ordering Code definition ..................................................29 Acronym ............................................................................30 Glossary ............................................................................31 Document History Page ...................................................32 Rev www.onsemi.com | Page NOII4SM6600A ...

Page 3

... Typical value of average dark current of the whole pixel array (at 21°C) Dark current RMS value (at 21°C) Measured at digital output (in the dark) Measured at digital output (in the dark) To the first neighboring pixel To the second neighboring pixel Typical (including ADCs) Rev www.onsemi.com | Page NOII4SM6600A Remarks Remarks Spectral Response Curve on page 4. ...

Page 4

... The sensor is light sensitive between 400 and 1000 nm. The peak QE × 25% approximately 650 nm. In view of a fill factor of 35%, the QE is close to 70% between 500 and 700 nm. Figure 2. Spectral Response Curve QE 20% 600 700 Wavelenght [nm] Rev www.onsemi.com | Page NOII4SM6600A QE 10% 800 900 1000 ...

Page 5

... Two on-chip 10-bit ADCs at 20 Msamples/s are multiplexed to one digital 10-bit output at 40 Msamples/s Nominal 2.5V (some supplies require 3.3V for extended dynamic range) 2.5V Serial-to Parallel Interface (SPI) 68-pins LCC Rev www.onsemi.com | Page NOII4SM6600A 20000 25000 Table 8 on page 12) ...

Page 6

... The IBIS4-6600 does not have latchup protection supply to digital circuit DDD DDA DDD [1,3] Description [2], [3] [4] Parameter or GND. The IBIS4-6600 is extremely susceptible to noise on the power supplies. In addition, DD Description DDA to analog circuit). DDA Rev www.onsemi.com | Page NOII4SM6600A Min Max - Min Max –0.5 4.3 –0 0.5) DD –0 0.5) DD –30 + ° ...

Page 7

... Most of the signals for the image core shown in generated on-chip by the sequencer. This sequencer also allows running the sensor in basic modes, not fully autonomous. Rev www.onsemi.com | Page NOII4SM6600A addres s & data bus Dig. logic (2) ...

Page 8

... In case of nondestructive readout (no double sampling), bus1_R and bus2_R are continuously connected to the output of the DAC_fine to provide a reference for the signals on bus1_S and bus2_S. Rev www.onsemi.com | Page NOII4SM6600A Dummy ring of pixels , s urrounding complete pixel array. not read R ing of dummy pixels , ...

Page 9

... The offset is 5.40 mainly given through DAC_raw. DAC_fine can be used to shift the reference voltage of bus down to compensate for 6.35 different offsets in the two channels. Rev www.onsemi.com | Page NOII4SM6600A output drivers Pixel output 1 Pixel output 2 1 Stage 2 ...

Page 10

... OUT VDDA 50K DAC_fine <0:7 out 50K rcal GNDA Note that in this figure, “K” represents K 1 00000000 ) (for example, for DAC_fine) out outfull = V /2 out outfull Rev www.onsemi.com | Page NOII4SM6600A blackref 10K bus1 200K blackref 10K bus2 200K ) ( 11111111 ) 8 2 ...

Page 11

... REG_CLOCK and become effective immediately. Figure 9. SPI Interface 16 outputs to address/data bus SPI_DATA SPI_CLK E ntire uploadable addres s block REG_CLOCK Dout SPI_CLK SPI_DATA A3 REG_CLOCK Rev www.onsemi.com | Page NOII4SM6600A Figure 9. Sixteen of these Internal register upload ...

Page 12

... The bits can be results in slightly different implementations of the sub-sampling Table 11 on modes for the two directions (Refer page 14). Table 8. Subsample Patterns Mode Rev www.onsemi.com | Page NOII4SM6600A Table 7 Comment Full resolution ROI read out 11 Figure 10 and Figure 11 Bits Read Step Description 000 ...

Page 13

... Figure 10. X-Sub Sampling scan direction Rev www.onsemi.com | Page column amplifiers NOII4SM6600A bus1_S bus1_R bus2_S bus2_R ...

Page 14

... Resolution (Y*X) Frame time [mS] 3002 x 2210 187.4 1502 x 1106 1002 x 738 752 x 554 502 x 370 640 x 480 663 x 503 480 x 640 503 x 663 Rev www.onsemi.com | Page NOII4SM6600A Frame time [mS] 5.3 52.3 19.1 25.7 38.9 15.8 63.2 8.2 121.2 12.3 81.5 13.1 76 ...

Page 15

... This is the case when FAST_RESET in the SEQUENCER register is set the nondestructive readout modes 1 and 2. Line number Figure 12. Electronic Shutter Figure 13. Electronic Rolling Shutter Operation Reset sequence Frame time Rev www.onsemi.com | Page NOII4SM6600A Figure 13, there are two Y shift registers. One Reset pointer Time axis Integration time ...

Page 16

... Figure 14. Double Slope Response Relative exposure (arbitrary scale) 20% 40% 60% Table 10 on page 17 summarizes the advantages and disadvantages of Figure 15. Principle of NonDestructive Readout Rev www.onsemi.com | Page NOII4SM6600A Dual slope operation Long integration time Short integration time 80% 100% time ...

Page 17

... Number of pixels to count (X direction). Max. 2222/2 (2210 real + 12 dummy pixels). Default value <10:0>:"01000000000" Rev www.onsemi.com | Page NOII4SM6600A Disadvantages ...

Page 18

... Delay of pixel clock to output amplifier Amplifier DAC raw offset Default value <7:0>:"10000000" Amplifier DAC fine offset Default value <7:0>:"10000000" DAC dark reference on output bus Default value <7:0>:"10000000" Rev www.onsemi.com | Page NOII4SM6600A ...

Page 19

... In setting 4, both rows are read out without being reset (on the 1 read first Y_CLOCK the row is read out by the left pointer; on the second Y_CLOCK the row is read out by the right pointer). 2 reset Rev www.onsemi.com | Page NOII4SM6600A Description Bits NDR mode Sequence read ...

Page 20

... INT_TIME register. At that moment, the YR_SYNC pulse for the right Y-shift register is generated, which loads the right Y-shift register with the pointer loaded in Y_REG register (shown in Rev www.onsemi.com | Page NOII4SM6600A Table 13 lists the settings for the Row Blanking Time [µs] 3.55 7 ...

Page 21

... Bits 2:7 of the IMAGE_CORE register define the sub sampling mode in the X-direction (bits 2:4) and in the Y-direction (bits 5:7). The sub sampling modes and corresponding bit setting are shown in “Subsampling Modes” Rev www.onsemi.com | Page NOII4SM6600A Last line, followed by sync of left shift-register Sync T int ...

Page 22

... Bitinvert If BITINVERT = 0, 0000000000 is the conversion of the lowest possible input voltage, otherwise the bits are inverted. Rev www.onsemi.com | Page NOII4SM6600A Table 15). The best setting also depends on the ...

Page 23

... These control signals must be generated by the external system with the following time constraints to SYS_CLOCK (rising edge = active edge): TSETUP >7.5 ns ■ THOLD > 7.5 ns ■ important that these signals are free of any glitches. Figure 18. Rev www.onsemi.com | Page NOII4SM6600A Table 13 on page 20). ...

Page 24

... The pixel signal at the OUT1 output becomes valid after five Figure 19). The SYS_CLOCK cycles when the internal X_SYNC (equal to start of PIXEL_VALID output) appears (see PIXEL_VALID and EOL/EOF pulses can be delayed by the user on page 20) through the DELAY register. T1: Row blanking time T2: 5 SYS_CLOCK cycles. Rev www.onsemi.com | Page NOII4SM6600A Figure 20). The ...

Page 25

... ADC using one analog output. Internally, the ADC samples on the falling edge of the ADC_CLOCK. T1: The ADC has a pipeline delay of 2 ADC_CLOCK cycles. Figure 21. ADC Timing using Two Analog Outputs Figure 22. ADC Timing using One Analog Output Rev www.onsemi.com | Page NOII4SM6600A ...

Page 26

... V DD Black level code 190 Analog output 2 DAC_RAW register See OUT2. Analog input ADC 2 2 digital part [2.5V GND (&substrate) of digital part Rev www.onsemi.com | Page NOII4SM6600A Pin Description with k and DDA with DDA with DDA ) DDA ) DDA ...

Page 27

... ADC data output - ADC data output - ADC data output - ADC data output - ADC data output 2.5 Reset voltage [2.5V]. Highest voltage to the chip. 3.3V for extended dynamic range or 'hard reset'. - ADC data output - ADC data output Rev www.onsemi.com | Page NOII4SM6600A Pin Description ...

Page 28

... Boundary scan (allows debugging of internal nodes): Bus. Leave floating if not used. 0.74 Biasing of X and Y decoder. Connect to V and decouple to GNDD with C = 100 nF therefore favorable to have separate analog and digital DDA Figure 23. 68 Pin LCC Packaging Outline Rev www.onsemi.com | Page NOII4SM6600A Pin Description with k DDD ...

Page 29

... The Product Acceptance Criteria is available on request. This document contains the criteria to which the IBIS4-6600 is tested before being shipped 6600 Rev www.onsemi.com | Page NOII4SM6600A shows the transmission characteristics of the glass lid. all image sensor products D C Commercial Temperature Range D= 263 Glass Q= LCC package Additional Functionality 6.6 MP Resolution ...

Page 30

... ROI region of interest ROT row overhead time S/H sample and hold SNR signal-to-noise ratio SPI serial peripheral interface TBD to be determined TIA Telecommunications Industry Association T Junction Temperature J TR training pattern % RH Percent Relative Humidity Rev www.onsemi.com | Page NOII4SM6600A Description ...

Page 31

... Signal-to-noise ratio. This number characterizes the ratio of the fundamental signal to the noise spectrum up to half the Nyquist frequency. temporal noise Noise that varies from frame to frame video stream, temporal noise is visible as twinkling pixels the units of sensitivity are quoted in V/lux/sec. Note Rev www.onsemi.com | Page NOII4SM6600A 1/683 W )/sec and are dependent on the ...

Page 32

... Document History Page Document Title: NOII4SM6600A 6.6 Megapixel CMOS Image Sensor Submission Rev. ECN Date ** 384900 See ECN *A 402976 See ECN *B 418669 See ECN *C 502551 See ECN *D 642596 See ECN *E 2649816 03/17/2009 PCI/AESA Final data sheet. Changed title from “IBIS4-A-6600 CMOS Image Sensor” to ...

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