NOIL2SM1300A-GWC ON Semiconductor, NOIL2SM1300A-GWC Datasheet - Page 11

• Manufacturer Part Number: NOIL2SM1300A-GWC
• Manufacturer: ON Semiconductor

Specifications of NOIL2SM1300A-GWC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

LVDS Block
receives a differential clock signal, transmits differential
data over the 12 data channels, and transmits a LVDS clock
signal and a synchronization signal over the clock and
synchronization channel.
block, serialize these bits, and converts them to an LVDS
standard (TIA/EIA 644A) compatible differential output
signal. The block must also provide a clock to the host, to
allow data recovery. This clock is an on-chip version of the
clock coming from the host.
Table 9. INTERNAL REGISTERS
MBS
(reserved)
LVDS clk
divider
AFE
The LVDS block is positioned below the data block. It
The function of this block is to take 10 bits of the protocol
Block
Fix1
Fix2
Fix3
Fix4
Fix5
lvdsmain
lvdspwd1
lvdspwd2
Fix6
afebias
afemode
afepwd1
Register Name
Transmitter
Serializer
Serializer
Serializer
LVDS
clock
Se rialize r<0 >
Se rialize r<0 >
Address [6..0]
Transmitter
LVDS
<0>
10
11
0
1
2
3
4
5
6
7
8
9
Figure 8. LVDS Block − High Level Overview
Serializer <1>
Serializer <1>
Transmitter
Field
LVDS
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:4]
[7:0]
[5:0]
[7:0]
[3:0]
[2:0]
[5:3]
[7:0]
<1>
[6]
[7]
[6]
http://onsemi.com
0x00
0xFF
0x00
0x00
0x08
‘0110’
0
0x00
0
0
0
0x00
‘1000’
‘111’
‘000’
0
0x00
Reset Value
…
…
Serializer <11>
Serializer <11>
11
Transmitter
LVDS
<11>
parallel to serve all data, clock, and synchronization output
channels. A high level overview is illustrated in the
following figure.
Sequencer and Logic
the pixel array and the readout. The timing can be controlled
by the user through the SPI register settings. The sequencer
operates on the same clock as the data block. This is a
division by 10 of the input clock (internally divided).
discussed in detail in Detailed Description of Internal
Registers on page 15.
A number of LVDS transmitter blocks are placed in
The sequencer generates the complete internal timing of
Table 9 lists the internal registers. These registers are
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
lvds trim
clkadc phase
Power down channel 7:0
Power down channel 13:8
Power down all channels
lvds test mode
Reserved, fixed value
afe current biasing
vrefp, vrefm settings
Pga settings
Power down AFE
Power down adc_channel_2x 7 to 0
cloc kge nerato r
cloc kge nerato r
Receiver
LVDS
Description
Transmitter
Se rializer
Se rializer
Se rializer
Synch
LVDS