LFXP6E-4Q208C Lattice, LFXP6E-4Q208C Datasheet - Page 199

• Manufacturer Part Number: LFXP6E-4Q208C
• Description: IC FPGA 5.8KLUTS 142I/O 208-PQFP
• Manufacturer: Lattice

Specifications of LFXP6E-4Q208C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Figures 9-33 to 9-36 show the behavior of non-pipelined FIFO or FIFO without output registers. When we pipeline
the registers, the output data is delayed by one clock cycle. There is an extra option of output registers being
enabled by RdEn signal.
Figures 9-37 to 9-40 show the similar waveforms for the FIFO with output register and without output register
enable with RdEn. It should be noted that flags are asserted and de-asserted with similar timing to the FIFO with-
out output registers. However it is only the data out 'Q' that gets delayed by one clock cycle.
Figure 9-37. FIFO with Output Registers, Start of Data Write Cycle
Almost
Almost
Empty
Empty
Reset
Clock
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
9-34
Invalid Q
Data_3
LatticeECP/EC and LatticeXP Devices
Data_4
Data_5
Memory Usage Guide