LFXP6E-4Q208C Lattice, LFXP6E-4Q208C Datasheet - Page 209
LFXP6E-4Q208C
Manufacturer Part Number
LFXP6E-4Q208C
Description
IC FPGA 5.8KLUTS 142I/O 208-PQFP
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP6E-4Q208C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
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LFXP6E-4Q208C
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Lattice Semiconductor
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based
PFU-based Distributed Single Port RAM is created using the 4-input LUT (Look-Up Table) available in the PFU.
These LUTs can be cascaded to create larger distributed memory sizes. The memory’s address and output regis-
ters are optional.
Figure 9-51 shows the Distributed Single Port RAM module as generated by the IPexpress.
Figure 9-51. Distributed Single Port RAM Module Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock, ClockEn and
Reset is generated by utilizing the resources available in the PFU. The basic Distributed Single Port RAM primitive
for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-52.
Figure 9-52. Distributed Single Port RAM (Distributed_SPRAM) for LatticeECP/EC and LatticeXP Devices
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants to enable the output registers in the IPexpress config-
uration.
The various ports and their definitions for the memory are included in Table 9-14. The table lists the corresponding
ports for the module generated by IPexpress and for the primitive.
AD[3:0]
ClockEn
Address
DI[1:0]
WRE
Reset
Clock
Data
CK
WE
Distributed Single Port
PFU
9-44
PFU based
Memory
LatticeECP/EC and LatticeXP Devices
DO[1:0]
Q
Memory Usage Guide
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