LFE2M20E-6F256C Lattice, LFE2M20E-6F256C Datasheet - Page 104

• Manufacturer Part Number: LFE2M20E-6F256C
• Description: IC FPGA 20KLUTS 140I/O 256-BGA
• Manufacturer: Lattice

Specifications of LFE2M20E-6F256C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
For Left and Right Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
For Bottom Edge of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
P[Edge] [n+4]
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 15 bits
PICs Associated with
of data for the left and right edges and up to 17 bits of data for the bottom edge. In some
packages, all the potential DDR data (DQ) pins may not be available. PIC numbering
definitions are provided in the “Signal Names” column of the Signal Descriptions table.
DQS Strobe
PIO Within PIC
4-4
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDR Strobe (DQS) and
LatticeECP2/M Family Data Sheet
Data (DQ) Pins
[Edge]DQSn
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Pinout Information