LFE2M20E-6F256C Lattice, LFE2M20E-6F256C Datasheet - Page 90

• Manufacturer Part Number: LFE2M20E-6F256C
• Description: IC FPGA 20KLUTS 140I/O 256-BGA
• Manufacturer: Lattice

Specifications of LFE2M20E-6F256C

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

Lattice Semiconductor
Table 3-9. SERDES/PCS Latency Breakdown (Parallel Clock Cycle)
Figure 3-12. Transmitter and Receiver Block Diagram
HDOUTPi
HDOUTNi
HDINPi
HDINNi
Transmit Data Latency
Receive Data Latency
1. PCS internal Parallel Clock. This clock rate is same as the rxfullclk in table 8-6.
2. FPGA Bridge latency varies by UP/DOWN Sample FIFO read/write. These numbers were presented for
3. The maximum latency applies to bit0.
Transmitter
Receiver
REFCLK
8bit/10bit interface. The depth of Down Sample/Up Sample FIFO is 4. The earliest read can be done after
write clock cycle (1 clock) in Down Sample FIFO. The latest read will be done after the FIFO is full (4 + 1
= 5). For 16b/20b interface, the numbers become doubled. Min = 2, Max = 10. This latency depends on
the internal FIFO flag operation.
Bit1 latency = Bit0 latency + 1 UI.
Bit2 latency = Bit0 latency + 2 UI.
Item
R1
R2
R3
R4
R5
R6
T1
T2
T3
T4
EQ
TX PLL
SERDES
FPGA Bridge Transmit
8b10b Encoder
SERDES Bridge Transmit
Serializer
Deserializer
SERDES Bridge Receive
Word Alignment
8b10b Decoder
Clock Tolerance Compensation
FPGA Bridge Receive
REFCLK
CDR
Serializer
8:1/10:1
Transmit Clock
T4
Deserializer
R1
1:8/1:10
3
Description
3
SERDES Bridge
R2
BYPASS
Polarity
Adjust
2
2
BYPASS
Polarity
Adjust
T3
Recovered Clock
3-39
BYPASS
Min.
R3
WA
1
2
2
2
4
1
7
1
Encoder
BYPASS
BYPASS
DEC
PCS
Average
T2
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
R4
15
3
2
2
2
4
1
3
BYPASS
Elastic
Buffer
FIFO
R5
Max.
2.4
1.2
23
5
2
2
2
4
1
5
FPGA Bridge
Sample
Down
FIFO
Sample
R6
FIFO
Up
BYPASS
Bypass
T1
1
1
1
1
0
1
1
1
FPGA Core
FPGA
EBRD Clock
Receive Data
FPGA
Receive Clock
Transmit Data
FPGA
Transmit Clock