LFE2-50E-5FN672C Lattice, LFE2-50E-5FN672C Datasheet - Page 58
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LFE2-50E-5FN672C
Manufacturer Part Number
LFE2-50E-5FN672C
Description
IC FPGA 50KLUTS 500I/O 672-BGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-5FN672C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Lattice Semiconductor
LatticeECP2M Initialization Supply Current
I
I
I
I
I
I
1. Until DONE signal is active.
2. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet.
3. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V
4. Frequency 0MHz.
5. T
6. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O con-
CC
CCAUX
CCGPLL
CCSPLL
CCIO
CCJ
figuration.
J
= 25
Symbol
o
C, power supplies at nominal voltage.
Core Power Supply Current
Auxiliary Power Supply Current
GPLL Power Supply Current (per GPLL)
SPLL Power Supply Current (per SPLL)
Bank Power Supply Current (per Bank)
VCCJ Power Supply Current
Over Recommended Operating Conditions
Parameter
3-7
1, 2, 3, 4
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2M100
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2M100
All Devices
All Devices
All Devices
All Devices
CCIO
Device
or GND.
Typ.
107
169
254
378
0.5
0.5
41
30
30
30
30
30
3
4
5, 6
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
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