LFE2-50E-7FN672C Lattice, LFE2-50E-7FN672C Datasheet - Page 21
LFE2-50E-7FN672C
Manufacturer Part Number
LFE2-50E-7FN672C
Description
IC FPGA 50KLUTS 500I/O 672-BGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-7FN672C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Part Number:
LFE2-50E-7FN672C
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Lattice Semiconductor Corporation
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Figure 2-19. Edge Clock Mux Connections
sysMEM Memory
LatticeECP2/M devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18-
Kbit RAM with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6. FIFOs can be implemented in sysMEM EBR blocks by imple-
menting support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for
each data byte. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths.
GPLL Output CLKOP
GPLL Output CLKOS
DLL Output CLKOP
DLL Output CLKOS
Clock Input Pad
GPLL Input Pad
GPLL Input Pad
Input Pad
Input Pad
Routing
Routing
Routing
CLKO
CLKO
2-18
Top and Bottom
ECLK1/ ECLK2
Left and Right
Left and Right
Edge Clocks
Edge Clocks
Edge Clocks
(Both Mux)
LatticeECP2/M Family Data Sheet
ECLK1
ECLK2
Architecture
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