LFE2-50E-7FN672C Lattice, LFE2-50E-7FN672C Datasheet - Page 97
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LFE2-50E-7FN672C
Manufacturer Part Number
LFE2-50E-7FN672C
Description
IC FPGA 50KLUTS 500I/O 672-BGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-7FN672C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-50E-7FN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 3-16. sysCONFIG Slave Serial Port Timing
Figure 3-17. Power-On-Reset (POR) Timing
Figure 3-18. Configuration from PROGRAMN Timing
V
V
1. Time taken from V
2. Device is in a Master Mode (SPI, SPIm).
3. The CFG pins are normally static (hard wired).
PROGRAMN
CCLK (input)
1. The CFG pins are normally static (hard wired)
CC
CCIO8
USER I/O
CFG[2:0]
CFG[2:0]
/ V
DONE
DONE
INITN
CCLK
CCAUX
1
INITN
CCLK
DOUT
DIN
2
3
1
/
CC
, V
CCAUX
t
t
DPPINIT
DINITD
or V
CCIO8
t
IODISS
, whichever is the last to cross the POR trip point.
t
PRGMRJ
t
ICFG
t
SUSCDI
t
VMC
3-46
t
SSCL
Valid
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
t
CODO
t
DINIT
t
SSCH
t
HSCDI
Valid
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