HI9P5043-5Z Intersil, HI9P5043-5Z Datasheet - Page 2
![IC SWITCH DUAL SPDT 16SOIC](/photos/5/65/56533/20-16-soic_sml.jpg)
HI9P5043-5Z
Manufacturer Part Number
HI9P5043-5Z
Description
IC SWITCH DUAL SPDT 16SOIC
Manufacturer
Intersil
Type
Analog Switchr
Datasheet
1.HI3-5043-5Z.pdf
(12 pages)
Specifications of HI9P5043-5Z
Function
Switch
Circuit
2 x SPDT
On-state Resistance
75 Ohm
Voltage Supply Source
Dual Supply
Voltage - Supply, Single/dual (±)
±14 V ~ 16 V
Operating Temperature
0°C ~ 75°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.154", 3.90mm Width)
Package
16SOIC N
Maximum On Resistance
75@±15V Ohm
Maximum High Level Output Current
30 mA
Number Of Channels Per Chip
2
Maximum Turn-on Time
500@±15V ns
Switch Architecture
SPDT
Power Supply Type
Dual
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HI9P5043-5Z
Manufacturer:
Intersil
Quantity:
1 864
Part Number:
HI9P5043-5Z
Manufacturer:
INTERSIL
Quantity:
20 000
Ordering Information
HI1-5042-2
HI1-5043-2
HI1-5043-5
HI3-5043-5
HI3-5043-5Z
(See Note)
HI9P5043-5
HI9P5043-5Z
(See Note)
HI1-5047-5
HI1-5049-5
HI1-5051-2
HI1-5051-5
HI3-5051-5
HI3-5051-5Z
(See Note)
HI9P5051-9
HI9P5051-9Z
(See Note)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PART NUMBER
RANGE (
-55 to 125
-55 to 125
-55 to 125
-40 to 85
-40 to 85
TEMP.
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
o
C)
2
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP*
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP *
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
PACKAGE
HI-5042 thru HI-5051
F16.3
F16.3
F16.3
E16.3
F16.3
M16.15
M16.15
F16.3
F16.3
F16.3
F16.3
E16.3
E16.3
M16.15
M16.15
DWG. #
PKG.
Pinouts
Single Control
NOTE: Unused pins may be internally connected. Ground all
unused pins.
Pinouts
Dual Control
NOTE: Unused pins may be internally connected. Ground all
unused pins.
HI-5043 (50Ω), HI-5051 (25Ω)
D
D
S
D
D
S
D
S
D
2
3
4
1
2
1
3
4
2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
HI-5042 (50Ω)
DUAL SPDT
SPDT
(SWITCHES SHOWN FOR LOGIC “0” INPUT)
(SWITCHES SHOWN FOR LOGIC “0” INPUT)
16
15
14
13
12
11
10
16
15
14
13
12
11
10
9
9
S
A
V-
V
V
V+
S
A
V-
V
V
V+
A
S
1
R
L
1
R
L
2
1
2
D
D
S
S
D
D
D
D
S
D
S
D
2
1
1
4
4
3
4
3
1
3
4
2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
HI-5047 (50Ω)
HI-5049 (25Ω)
DUAL DPST
4PST
16
15
14
13
12
11
10
16
15
14
13
12
11
10
9
9
S
A
V-
V
V
V+
S
S
A
V-
V
V
V+
A
S
2
R
L
3
1
1
R
L
2
2