ISL97671AIRZ-T Intersil, ISL97671AIRZ-T Datasheet - Page 19

• Manufacturer Part Number: ISL97671AIRZ-T
• Description: IC LED DRVR 6-CH BACKLIGHT 20QFN
• Manufacturer: Intersil
• Series: -r

Specifications of ISL97671AIRZ-T

• Constant Current: -
• Constant Voltage: -
• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB
• Frequency: 475kHz ~ 640kHz, 970kHz ~ 1.31MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Voltage - Output: 45V
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: ISL97671AIRZ-TTR

PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM duty cycle
adjustment. Figure 30 shows the bit assignment. All of the bits in
this Brightness Control Register can be read or write. Step 0
corresponds to the minimum step where the current is less than
10µA. Steps 1 to 255 represent the linear steps between 0.39% and
100% duty cycle with approximately 0.39% duty cycle adjustment
per step.
• An SMBus/I
ADDRESS
ADDRESS
brightness level only if the backlight controller is in SMBus/I
mode (see Table 4) Operating Modes selected by Device
Control Register Bits 1 and 2).
0x03
0x07
0x08
0x09
0x0A
0x00
0x01
0x02
0x03
0x07
0x08
0x09
0x0A
Control Register
Phase Shift Deg
Output Channel
DC Brightness
Configuration
Identification
PWM Brightness Control
Register
Device Control Register
Fault/Status Register
Identification Register
DC Brightness Control Register
Configuration Register
Output Channel Mask/Fault
Readout Register
Phase Shift Degree
REGISTER
2
Register
Register
Register
C Write Byte cycle to Register 0x00 sets the PWM
REGISTER
LED PANEL
Reserved
Reserved
BRTDC7
Phase
Equal
BIT 7
19
DirectPWM
Reserved
BRTDC6
Phase
MFG3
Shift6
BIT 6
TABLE 3A. ISL97671A REGISTER LISTING
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change), default = 0
PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by SMBus/I
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
BRTDC[7..0] = 256 steps of DC brightness control
DirectPWM = Forces the PWM input signal to directly control the current sources.
Bits 3, 4, and 5 should be 1, 1, 0
FSW = Switching frequencies selection, FSW = 0 = 1.2MHz. FSW = 1 = 600kMHz
VSC[0] = Short circuit thresholds selection, 0 = disabled, 1 = 7.2V minimum
CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In
Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled
EqualPhase = Controls phase shift mode - When 1, phase shift is 360/N (where N is the number of
channels enabled). When 0, phase shift is defined by PhaseShift<6:0>.
PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is
PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each channel is
PhaseShift<6:0>/12.8MHz.
BRTDC5
Phase
MFG2
Shift5
BIT 5
CH5
TABLE 3B. DATA BIT DESCRIPTIONS
0
ISL97671A
BRTDC4
Phase
MFG1
Shift4
BIT 4
CH4
1
2
C
BRTDC3
• An SMBus/I
• An SMBus/I
• An SMBus/I
• Default value for Register 0x00 is 0xFF.
Phase
MFG0
Shift3
BIT 3
CH3
1
programmed PWM brightness level.
backlight controller to the maximum brightness.
backlight controller to the minimum brightness output.
DATA BIT DESCRIPTIONS
BRTDC2
Phase
Shift2
REV2
BIT 2
FSW
CH2
(Continued)
2
2
2
C Read Byte cycle to Register 0x00 returns the
C setting of 0xFF for Register 0x00 sets the
C setting of 0x00 for Register 0x00 sets the
Reserved
BRTDC1
Phase
Shift1
REV1
BIT 1
CH1
BRTDC0
Phase
Shift0
REV0
BIT 0
CH0
VSC
DEFAULT
VALUE
0xC8
0x1F
0x3F
0x00
0xFF
2
C), default = 0
Read and Write
Read and Write
Read and Write
Read and Write
March 24, 2011
SMBUS/I
PROTOCOL
Read Only
FN7709.1
2
C