PC28F512P30EFA Micron Technology Inc, PC28F512P30EFA Datasheet - Page 35

• Manufacturer Part Number: PC28F512P30EFA
• Manufacturer: Micron Technology Inc

Specifications of PC28F512P30EFA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: BGA
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

P30-65nm
11.2
Table 13: Read Configuration Register Description (Sheet 1 of 2)
Datasheet
35
Read Configuration Register (RCR)
15
14:11
10
9
8
7
6
5:4
Mode
Read
RM
15
Bit
Read Mode (RM)
Latency Count (LC[3:0])
WAIT Polarity (WP)
Reserved (R)
WAIT Delay (WD)
Burst Sequence (BS)
Clock Edge (CE)
Reserved (R)
14
Latency Count
Read Configuration Register (RCR) (Easy BGA)
The RCR is a 16-bit read/write register used to select bus-read mode (synchronous or
asynchronous), and to configure synchronous burst read characteristics of the device.
To modify RCR settings, use the Configure Read Configuration Register command (see
Section 6.2, “Device Command Bus Cycles” on page
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see
Upon power-up or exit from reset, the RCR defaults to asynchronous mode.
The RCR is shown in
13
LC[3:0]
Name
12
11
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
0011 =Code 3
0100 =Code 4
0101 =Code 5
0110 =Code 6
0111 =Code 7
1000 =Code 8
1001 =Code 9
1010 =Code 10
1011 =Code 11
1100 =Code 12
1101 =Code 13
1110 =Code 14
1111 =Code 15 (default)
(Other bit settings are reserved)
0 =WAIT signal is active low (default)
1 =WAIT signal is active high
Default “0”, Non-changeable
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
Default “0”, Non-changeable
0 = Falling edge
1 = Rising edge (default)
Reserved bits should be cleared (0)
Polarity
WAIT
WP
10
Table
RES
13. The following sections describe each RCR bit function.
R
9
Section 7.2, “Read Device Identifier” on page
Delay
WAIT
WD
8
Burst
Seq
BS
7
Edge
CLK
CE
6
Description
RES
20).
R
5
RES
R
4
Burst
Wrap
BW
3
Order Number:208042-05
2
Burst Length
BL[2:0]
22).
1
Apr 2010
0