PC28F512P30EFA Micron Technology Inc, PC28F512P30EFA Datasheet - Page 56

• Manufacturer Part Number: PC28F512P30EFA
• Manufacturer: Micron Technology Inc

Specifications of PC28F512P30EFA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: BGA
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

Table 26: AC Write Specifications (Sheet 2 of 2)
Figure 24: Write-to-Write Timing
Datasheet
56
Write to Synchronous Read Specifications
W19
W20
W28
Write Specifications with Clock Active
W21
W22
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Address [A]
Num
Data [D/Q]
RST# [P]
WE# [W]
OE# [G]
CE# [E]
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
(whichever occurs first). Hence, t
Write pulse width high (t
(whichever occurs last). Hence, t
t
VPP and WP# should be at a valid level until erase or program success is determined.
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20ns.
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
These specs are required only when the device is in a synchronous mode and clock is active during address setup
phase.
These specs are required only when ADV# is used to latch address.
This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation
to this timing specification.
WHVH
t
t
t
t
t
WHCH/L
WHVH
WHVL
VHWL
CHWL
Symbol
or t
WHCH/L
W1
W2
WE# high to Clock valid
WE# high to ADV# high
WE# high to ADV# low
ADV# high to WE# low
Clock high to WE# low
must be met when transiting from a write cycle to a synchronous burst read.
WLWH
WHWL
W5
or t
or t
W3
W3
ELEH
WHWL
WLWH
EHEL
Parameter
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
= t
= t
W4
EHEL
ELEH
= t
= t
WHEL
WLEH
W7
W6
W8
= t
= t
EHWL
W9
W9
ELWH
).
.
W2
Min
W5
19
19
7
-
-
W3
W3
W4
Max
20
20
-
-
-
Order Number: 208042-05
Unit
W7
W6
ns
ns
ns
ns
ns
W8
1,2,3,6,10,12
1,2,3,11,12
1,2,3,6,10
1,2,3,11
P30-65nm
Notes
Apr 2010