XRP7714ILB-0X14-F Exar Corporation, XRP7714ILB-0X14-F Datasheet - Page 18

• Manufacturer Part Number: XRP7714ILB-0X14-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Series: -r

Specifications of XRP7714ILB-0X14-F

• Topology: Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 5
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 4.75 V ~ 25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1700

When an over-current condition occurs, PWM drivers in the corresponding channels are disabled.
After a 200ms timeout, the controller is re-powered and soft-start is initiated. When the over-
current condition is reached the controller will check the SET_FAULT_RESP_CONFIG_LB and
SET_FAULT_RESP_CONFIG_HB to determine whether there are any “following” channels that need
to be similarly restarted. The controller will also set the fault flags in READ_OVC_FAULT_WARN
register.
Typically the over-current fault threshold would be set to 130-140% of the maximum desirable
output current. This will help avoid any over-current conditions caused by transients that would
shut down the output channel.
CHIP OPERATION AND CONFIGURATION
S
The SET_SS_RISE_CHx register is a 16 bit register which specifies the soft-start delay and the
ramp characteristics for a specific channel. This register allows the customer to program the
channel with a 250µs step resolution and up to a maximum 16ms delay.
Bits [15:10] specify the delay after enabling a channel but before outputting pulses; where each bit
represents 250µs steps. Bits [9:0] specify the rise time of the channel; these 10 bits define the
number of microseconds for each 50mV increment to reach the target voltage.
© 2011 Exar Corporation
Over-Current Fault Handling
OFT
-S
TART
Enable
Signal
Vout
Q
Q
Fig. 24: Channel Power Up Sequence
u
u
a
a
d
Bit [10:15]
d
DELAY
C
C
h
h
a
a
18/29
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n
SS_RISE_CHx
REGISTER
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e
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l
D
D
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g
g
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i
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t
a
a
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P
P
W
W
RISE TIME
Bit [0:9]
M
M
S
S
t
t
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e
p
p
D
D
o
o
w
w
n
n
X
X
C
C
R
R
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P
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P
Rev. 1.1.6
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7
7
r
r
o
o
7
7
l
l
1
1
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4
4
r
r