AT45DB161D-SU-2.5 SL383 Atmel, AT45DB161D-SU-2.5 SL383 Datasheet - Page 4

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AT45DB161D-SU-2.5 SL383

Manufacturer Part Number
AT45DB161D-SU-2.5 SL383
Description
Manufacturer
Atmel
Datasheet

Specifications of AT45DB161D-SU-2.5 SL383

Density
16Mb
Access Time (max)
6ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC EIAJ
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Supply Current
15mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Compliant
3.
4.
Figure 4-1.
4
SECTOR ARCHITECTURE
Block Diagram
Memory Array
To provide optimal flexibility, the memory array of the Atmel
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the
breakdown of each level and details the number of pages per sector and block. All program operations to the Atmel
DataFlash
page level.
RDY/BUSY
Atmel AT45DB161D
SECTOR 14 = 256 Pages
SECTOR 15 = 256 Pages
SECTOR 1 = 256 Pages
SECTOR 2 = 256 Pages
131,072-/135,168-bytes
131,072-/135,168-bytes
131,072-/135,168-bytes
SECTOR 0b = 248 Pages
131,072-/135,168-bytes
SECTOR 0a = 8 Pages
126,976-/130,944-bytes
4,096-/4,224-bytes
RESET
Memory Architecture Diagram
GND
VCC
SCK
WP
CS
®
occur on a page by page basis. The erase operations can be performed at the chip, sector, block or
BUFFER 1 (512-/528-BYTES)
PAGE (512-/528-BYTES)
SECTOR 0
SI
BLOCK ARCHITECTURE
Block = 4,096-/4,224-bytes
FLASH MEMORY ARRAY
BLOCK 510
BLOCK 511
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
I/O INTERFACE
®
AT45DB161D is divided into three levels of
8 Pages
BUFFER 2 (512-/528-BYTES)
SO
PAGE ARCHITECTURE
Page = 512-/528-bytes
PAGE 4,094
PAGE 4,095
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
3500N–DFLASH–05/10

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