PCA8581P NXP Semiconductors, PCA8581P Datasheet - Page 6

• Manufacturer Part Number: PCA8581P
• Manufacturer: NXP Semiconductors

Specifications of PCA8581P

• Density: 1Kb
• Interface Type: Serial (I2C)
• Organization: 128x8
• Access Time (max): 3.4us
• Frequency (max): 100KHz
• Write Protection: No
• Data Retention: 10Year
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Temp Range: -25C to 85C
• Supply Current: 1mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.3
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
7.4
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
1997 Apr 02
handbook, full pagewidth
128
System configuration
Acknowledge
SDA
SCL
8-bit EEPROM with I
BY TRANSMITTER
TRANSMITTER /
DATA OUTPUT
DATA OUTPUT
RECEIVER
BY RECEIVER
MASTER
SCL FROM
MASTER
condition
START
S
RECEIVER
Fig.6 Acknowledgement on the I
SLAVE
2
C-bus interface
Fig.5 System configuration.
1
TRANSMITTER /
RECEIVER
2
6
SLAVE
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
2
C-bus.
TRANSMITTER
MBA606 - 1
MASTER
8
PCA8581; PCA8581C
acknowledgement
clock pulse for
9
TRANSMITTER /
RECEIVER
MASTER
Product specification
MBA605