IDT82V3002APV IDT, Integrated Device Technology Inc, IDT82V3002APV Datasheet - Page 16

• Manufacturer Part Number: IDT82V3002APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3002APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

respectively.
3.7.5
from Loop Filter or Fraction blocks. Based on the received signals, the
DCO generates three digital outputs, 25.248 MHz, 32.768 MHz and
24.704 MHz for C6, E1 and T1 divider respectively.
is generated by using the storage techniques.
of the master clock.
3.7.6
following equation is satisfied:
(within 2 seconds)
3.7.7
generate eight types of clock signals and six types of framing signals
totally.
types of clock signals (C2o, C4o, C8o, C16o and C32o) with nominal
50% duty cycle and six types of framing signals (F0o, F8o, F16o, F32o,
RSP and TSP).
types of T1 signals (C1.5o and C3o) with nominal 50% duty cycle.
signal with nominal 50% duty cycle.
3.8
identical to that of the source at the OSCi pin. For applications not
requiring an accurate Freerun Mode, the tolerance of the master timing
source may be ±100 ppm. For applications requiring an accurate
Freerun Mode, such as AT&T TR62411, the tolerance of the master
timing source must be no greater than ±32 ppm.
determining the accuracy of the master timing source. The sum of the
accuracy of the master timing source and the capture range of the
IDT82V3002A will always equal 230 ppm. For example, if the master
timing source is 100 ppm, the capture range will be 130 ppm.
3.8.1
FUNCTIONAL DESCRIPTION
IDT82V3002A
In Normal Mode, the DCO receives three limited and filtered signals
In Holdover mode, the DCO is running at the same frequency which
In Freerun mode, the DCO is running at the same frequency as that
In Normal Mode, the LOCK pin will be set to high only when the
f
f
In other operation modes, the LOCK pin remains low.
The Output Interface uses three output signals of the DCO to
The 32.768 MHz signal is used by the E1_divider to generate five
The 24.704 MHz signal is used by the T1_divider to generate two
The 25.248 MHz signal is used by the C6_divider to generate a C6o
All these output signals are synchronous to F8o.
The IDT82V3002A can use a clock as the master timing source.
In Freerun Mode, the frequency tolerance at the clock outputs is
The desired capture range should be taken into consideration when
When selecting a clock oscillator, numerous parameters must be
out
in
= the average frequency of the input reference (within 2 seconds)
= the average frequency of the output clock signal from the DPLL
DIGITAL CONTROL OSCILLATOR (DCO)
LOCK INDICATOR
OUTPUT INTERFACE
OSC
CLOCK OSCILLATOR
|f
out
– f
in
| ≤ 0.4 ppm
16
considered, including absolute frequency, frequency change over
temperature, output rise and fall times, output levels and duty cycle.
clock oscillator module may be used.
the OSCi input of the IDT82V3002A, and the OSCo output should be left
open as shown in
3.9
3.10
used for protection only and limits current into the RST pin during power
down conditions. The reset low time is not critical but should be greater
than 300 ns. In
For applications requiring ±32 ppm clock accuracy, the following
FOX F7C-2E3-20.0 MHz
Frequency:
Tolerance:
Rise & Fall Time:10 ns (0.33 V 2.97 V 15 pF)
Duty Cycle:
The output clock should be connected directly (not AC coupled) to
The IDT82V3002A supports IEEE 1149.1 JTAG Scan.
A simple power up reset circuit is shown in
JTAG
RESET CIRCUIT
Figure -
Figure - 10 Power-Up Reset Circuit
Figure - 9 Clock Oscillator Circuit
IDT82V3002A
Figure -
WAN PLL WITH DUAL REFERENCE INPUT
20 MHz
25 ppm 0°C to 70°C
40% to 60%
OSCi
OSCo
No Connection
IDT82V3002A
10, the reset low time is about 50 µs.
9.
RST
1 kΩ
Rp
20 MHz OUT
+3.3 V
+3.3 V
GND
10 kΩ
Figure -
R
3.3 V
October 15, 2008
10. Resistor Rp is
1 µF
C
0.1 µF