CY7C144-35AC Cypress Semiconductor Corp, CY7C144-35AC Datasheet - Page 14

• Manufacturer Part Number: CY7C144-35AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C144-35AC

• Density: 64Kb
• Access Time (max): 35ns
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 160mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Word Size: 8b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06034 Rev. *C
Architecture
The CY7C144/5 consists of a an array of 8K words of 8/9 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S
pin, the CY7C144/5 can function as a Master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). The CY7C144/5
has an automatic power-down feature controlled by CE. Each
port is provided with its own output enable control (OE), which
allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W in order to guarantee a valid write. A write operation is
controlled by either the OE pin (see Write Cycle No.1
waveform) or the R/W pin (see Write Cycle No. 2 waveform).
Data can be written to the device t
deasserted or t
inputs for non-contention operations are summarized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
OE are asserted. If the user of the CY7C144/5 wishes to
access a semaphore flag, then the SEM pin must be asserted
instead of the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s
interrupt flag (INT
port reads that same location. Setting the left port’s interrupt
flag (INT
location 1FFE. This flag is cleared when the left port reads
location 1FFE. The message at 1FFF or 1FFE is user-defined.
See Table 2 for input requirements for INT. INT
push-pull outputs and do not require pull-up resistors to
operate.
Busy
The CY7C144/5 provides on-chip arbitration to alleviate simul-
taneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within t
each other the Busy logic will determine which port has
access. If t
permission to the location, but it is not guaranteed which one.
BUSY will be asserted t
after CE is taken LOW. BUSY
are push-pull outputs and do not require pull-up resistors to
operate.
L
) is accomplished when the right port writes to
DDD
PS
HZWE
after the data is presented on the other port.
is violated, one port will definitely gain
R
) is set. This flag is cleared when the right
after the falling edge of R/W. Required
BLA
after an address match or t
L
and BUSY
ACE
SD
HZOE
before the rising edge
after CE or t
R
after the OE is
in master mode
R
and INT
DOE
PS
L
after
BLC
are
of
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components.Writing of slave devices must be
delayed until after the BUSY input has settled. Otherwise, the
slave chip may begin a write cycle during a contention
situation.When presented a HIGH input, the M/S pin allows the
device to be used as a master and therefore the BUSY line is
an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphore Operation
The CY7C144/5 provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for t
The semaphore value will be available t
rising edge of the semaphore write. If the left port was
successful (reads a 0), it assumes control over the shared
resource, otherwise (reads a 1) it assumes the right port has
control and continues to poll the semaphore.When the right
side has relinquished control of the semaphore (by writing a
1), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore,
a 1 is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE and R/W are used in the same
manner as a normal memory access.When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an unused semaphore, a 1 will appear
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing 0
(the left port in this case). If the left port now relinquishes
control by writing a 1 to the semaphore, the semaphore will be
set to 1 for both sides. However, if the right port had requested
the semaphore (written a 0) while the left port had control, the
right port would immediately own the semaphore as soon as
the left port released it. Table 3 shows sample semaphore
operations.
When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within t
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
Initialization of the semaphore is not automatic and must be
reset
Semaphores on both sides should have a one written into
them at initialization from both sides to assure that they will be
free when needed.
during
SOP
initialization
before attempting to read the semaphore.
SPS
of each other, the semaphore will
program
SWRD
at
0
0–2
is used. If a 0 is
CY7C144
CY7C145
+ t
power-up.
represents the
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DOE
after the
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