TDA4857PS NXP Semiconductors, TDA4857PS Datasheet - Page 9

• Manufacturer Part Number: TDA4857PS
• Manufacturer: NXP Semiconductors

Specifications of TDA4857PS

• Lead Free Status / Rohs Status: Not Compliant

Philips Semiconductors
Output stage for line drive pulses [HDRV (pin 8)]
An open-collector output stage allows direct drive of an
inverting driver transistor because of a low saturation
voltage of 0.3 V at 20 mA. To protect the line deflection
transistor, the output stage is disabled (floating) for a low
supply voltage at V
The duty cycle of line drive pulses is slightly dependent on
the actual horizontal frequency. This ensures optimum
drive conditions over the whole frequency range.
X-ray protection
The X-ray protection input XRAY (pin 2) provides a voltage
detector with a precise threshold. If the input voltage at
XRAY exceeds this threshold level for a certain time then
control bit SOFTST is reset, which switches the IC into
protection mode. In this mode several pins are forced into
defined states:
There are two different methods of restarting the IC:
1. XSEL (pin 9) is open-circuit or connected to ground.
2. XSEL (pin 9) is connected to V
Vertical oscillator and amplitude control
This stage is designed for fast stabilization of vertical size
after changes in sync frequency conditions.
The free-running frequency f
resistor R
C
optimized for noise and linearity performance in the whole
vertical and EW section, but also influences several
internal references. Therefore the value of R
be changed.
2001 Apr 11
VCAP
HUNLOCK (pin 17) is floating
The capacitor connected to HPLL2 (pin 30) is
discharged
Horizontal output stage (HDRV) is floating
B+ control driver stage (BDRV) is floating
Vertical output stages (VOUT1 and VOUT2) are floating
CLBL provides a continuous blanking signal.
I
PC monitors
2
The control bit SOFTST must be set to logic 1 via the
I
soft start.
resistor. The supply voltage of the IC must be switched
off for a certain period of time before the IC can be
restarted again using the standard power-on
procedure.
2
C-bus autosync deflection controller for
C-bus. The IC then returns to normal operation via
connected to pin 24. The value of R
VREF
connected to pin 23 and the capacitor
CC
(see Fig.24).
fr(V)
is determined by the
CC
via an external
VREF
VREF
is not only
must not
9
Capacitor C
frequency of the vertical oscillator in accordance with the
following formula:
To achieve a stabilized amplitude the free-running
frequency f
lower than the minimum trigger frequency.
The contributions shown in Table 2 can be assumed.
Table 2 Calculation of f
Result for 50 to 160 Hz application:
The AGC of the vertical oscillator can be disabled by
setting control bit AGCDIS via the I
external current has to be injected into VCAP (pin 24) to
obtain the correct vertical size. This special application
mode can be used when the vertical sync pulses are
serrated (shifted); this condition is found in some display
modes, e.g. when using a 100 Hz upconverter for video
signals.
Application hint: VAGC (pin 22) has a high input
impedance during scan. Therefore, the pin must not be
loaded externally otherwise non-linearities in the vertical
output currents may occur due to the changing charge
current during scan.
Adjustment of vertical size, VGA overscan and EHT
compensation
The amplitude of the differential output currents at VOUT1
and VOUT2 can be adjusted via register VSIZE. Register
VOVSCN can activate a +17% step in vertical size for the
VGA350 mode.
VSMOD (pin 21) can be used for a DC controlled EHT
compensation of vertical size by correcting the differential
output currents at VOUT1 and VOUT2. The EW
waveforms, vertical focus, pin unbalance and
parallelogram corrections are not affected by VSMOD.
f
Minimum frequency offset between f
lowest trigger frequency
Spread of IC
Spread of R
Spread of C
Total
fr V
=
50 Hz
-------------- -
1.19
fr(V)
Contributing elements
VCAP
VREF
VCAP
, without adjustment, should be at least 10%
=
should be used to select the free-running
42 Hz
f
fr V
=
fr(V)
---------------------------------------------------------- -
10.8 R
total spread
2
VREF
C-bus. A precise
TDA4857PS
Product specification
fr(V)
1
and
C
VCAP
10%
19%
3%
1%
5%