IDTQS5LV919-133Q IDT, Integrated Device Technology Inc, IDTQS5LV919-133Q Datasheet - Page 8

• Manufacturer Part Number: IDTQS5LV919-133Q
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of IDTQS5LV919-133Q

• Number Of Elements: 1
• Pll Input Freq (min): 2.5MHz
• Pll Input Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: QSOP
• Output Frequency Range: 5 to 133MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The
Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run
at 2X the Q frequency.
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q
frequency will equal the SYNC frequency. The Q/2 output will always run at
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Note that with 2Q as feedback, the maximum input frequency is 100MHz for FS
= HIGH
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1,
Q2, Q3 and Q4).
50 MHz
input
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
Figure 2a. Wiring Diagram and Frequency Relationships with 2Q
In this application, the Q4 output is connected to the FEEDBACK input. The
In this application, the 2Q output is connected to the FEEDBACK input. The
LOW
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
FEEDBACK
REF_SEL
SYNC(0)
V
GND(AN)
FQ_SEL
PE
50 MHz feedback signal
OE/
CC
HIGH
HIGH
(AN)
RST
Q5
Q0
Output Feedback
QS5LV919
Q1
Q4
PLL_EN
HIGH
2Q
Q/2
Q3
Q2
12.5 MHz
input
25 MHz
Outputs
Clock
"Q"
8
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2
frequency.
25 MHz
input
12.5 MHz
input
LOW
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
In this application, the Q/2 output is connected to the FEEDBACK input. The
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Figure 2c. Wiring Diagram and Frequency Relationships with
Figure 2b. Wiring Diagram and Frequency Relationships with
LOW
25 MHz feedback signal
FEEDBACK
REF_SEL
SYNC(0)
V
PE
GND(AN)
FQ_SEL
OE/
HIGH
HIGH
CC
FEEDBACK
REF_SEL
SYNC(0)
V
GND(AN)
FQ_SEL
PE
OE/
HIGH
CC
HIGH
(AN)
12.5 MHz feedback signal
RST
(AN)
RST
Q2 Output Feedback
Q4 Output Feedback
Q0
Q5
Q5
Q0
QS5LV919
QS5LV919
INDUSTRIAL TEMPERATURE RANGE
Q1
Q4
Q1
Q4
PLL_EN
PLL_EN
HIGH
2Q
HIGH
50 MHz signal
2Q
50 MHz signal
Q/2
Q3
Q2
Q/2
Q3
Q2
12.5 MHz
signal
25 MHz
Outputs
25 MHz
Outputs
Clock
Clock
"Q"
"Q"