A54SX08A-FTQ100 MICROSEMI, A54SX08A-FTQ100 Datasheet - Page 54

• Manufacturer Part Number: A54SX08A-FTQ100
• Manufacturer: MICROSEMI

Specifications of A54SX08A-FTQ100

• Family Name: SX-A
• Number Of Usable Gates: 8000
• Number Of Logic Blocks/elements: 768
• # Registers: 512
• # I/os (max): 81
• Frequency (max): 172MHz
• Process Technology: 0.25um/0.22um (CMOS)
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 512
• Device System Gates: 12000
• Propagation Delay Time: 1.7ns
• Operating Supply Voltage (min): 2.25V
• Operating Supply Voltage (max): 2.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Table 2-28 • A54SX32A Timing Characteristics
2 -3 4
Parameter
C-Cell Propagation Delays
t
Predicted Routing Delays
t
t
t
t
t
t
t
t
R-Cell Timing
t
t
t
t
t
t
t
t
t
Input Module Propagation Delays
t
t
t
t
t
t
Notes:
1. All –3 speed grades have been discontinued.
2. For dual-module macros, use t
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
PD
DC
FC
RD1
RD2
RD3
RD4
RD8
RD12
RCO
CLR
PRESET
SUD
HD
WASYN
RECASYN
HASYN
MPW
INYH
INYL
INYH
INYL
INYH
INYL
SX-A Family FPGAs
performance. Post-route timing analysis or simulation is required to determine actual performance.
(Worst-Case Commercial Conditions, V
Internal Array Module
FO = 1 Routing Delay, Direct
Connect
FO = 1 Routing Delay, Fast Connect
FO = 1 Routing Delay
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
Sequential Clock-to-Q
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Clock Pulse Width
Input Data Pad to Y High 2.5 V
LVCMOS
Input Data Pad to Y Low 2.5 V
LVCMOS
Input Data Pad to Y High 3.3 V PCI
Input Data Pad to Y Low 3.3 V PCI
Input Data Pad to Y High 3.3 V
LVTTL
Input Data Pad to Y Low 3.3 V LVTTL
Description
3
2
PD
+ t
RD1
+ t
PDn
, t
RCO
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
–3 Speed
0.6
0.0
0.3
0.3
1.4
1.2
CCA
+ t
RD1
= 2.25 V
0.8
0.1
0.3
0.3
0.4
0.5
0.7
1.2
1.7
0.6
0.5
0.6
0.6
1.2
0.5
0.6
0.8
1.4
+ t
1
v5.3
PDn
,
–2 Speed
0.7
0.0
1.4
0.4
0.3
1.6
V
, or t
CCI
= 3.0 V, T
PD1
0.9
0.1
0.3
2.0
0.7
0.7
1.3
0.6
0.7
0.9
0.3
0.5
0.6
0.8
1.4
0.6
0.7
1.6
+ t
RD1
0.8
0.0
1.5
0.4
0.3
1.8
–1 Speed
J
+ t
= 70°C)
SUD
1.1
0.1
0.3
0.4
0.5
0.7
0.9
1.5
2.2
0.8
0.6
0.7
0.8
1.5
0.6
0.8
1.0
1.8
, whichever is appropriate.
Std. Speed
0.9
0.0
1.8
0.5
0.4
2.1
1.2
0.1
0.4
0.5
0.6
0.8
1.0
1.8
2.6
0.9
0.8
0.9
0.9
1.8
0.7
0.9
1.2
2.2
1.2
0.0
2.5
0.7
0.6
2.9
–F Speed
1.7
0.1
0.6
0.6
0.8
1.1
1.4
2.5
3.6
1.3
1.0
1.2
1.2
2.5
1.0
1.3
1.6
3.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns