MB91F376G Fujitsu Components, MB91F376G Datasheet - Page 165

• Manufacturer Part Number: MB91F376G
• Manufacturer: Fujitsu Components

Specifications of MB91F376G

• Lead Free Status / Rohs Status: Not Compliant

20. 16-bit I/O Timer
(1) Function overview
The MB91360G Series contains two 16-bit free-running timer modules, two output compare modules, and two
input capture modules and supports four input channels and four output channels. The following sections only
describes the 16-bit free-running timer, Output Compare 0/1 and Input Capture 0/1.
The remaining modules have the identical functions and the register addresses should be found in the I/O map.
a : 16-bit free-running timer
The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The values output from
this timer counter are used as the base timer for input capture and output compare.
• Four counter clocks are available.
• An interrupt can be generated upon a counter overflow or a match with compare register 0.
• The counter value can be initialized to “0000H” upon a reset, software clear, or match with compare register 0.
b : Output compare (2 channels per one module)
The output compare module consists of two 16-bit compare registers, compare output latch, and control register.
When the 16-bit free-running timer value matches the compare register value, the output level is reversed and
an interrupt is issued.
• The two compare registers can be used independently.
• Output pins can be controlled based on pairs of the two compare registers.
• Initial values for output pins can be set.
• Interrupts can be generated upon a compare match.
c : Input capture (2 channels per one module)
The input capture module consists of two 16-bit capture registers and control registers corresponding to two
independent external input pins. The 16-bit free-running timer value can be stored in the capture register and
an interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin.
• The detection edge of an external input signal can be specified.
• Two input channels can operate independently.
• An interrupt can be issued upon a valid edge of an external input signal.
Internal clock : φ/4, φ/16, φ/32, φ/64
Output pins and interrupt flags corresponding to compare registers
Output pins can be reversed by using the two compare registers.
Rising, falling, or both edges
MB91360G Series
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