PCF8566T NXP Semiconductors, PCF8566T Datasheet - Page 21

• Manufacturer Part Number: PCF8566T
• Manufacturer: NXP Semiconductors

Specifications of PCF8566T

• Operating Supply Voltage (typ): 3.3/5V
• Number Of Digits: 12
• Number Of Segments: 96
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: VSO
• Pin Count: 40
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Frequency (max): 315KHz
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 6V
• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
PCF8566_7
Product data sheet
8.1.1.1 START and STOP conditions
8.1.2 System configuration
8.1.3 Acknowledge
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in
A device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is illustrated in
Figure
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse. (See
Figure
Acknowledgement on the I
Fig 13. Definition of START and STOP conditions
Fig 14. System configuration
•
•
•
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
SCL
SDA
SDA
SCL
14.
15).
TRANSMITTER/
RECEIVER
MASTER
START condition
S
Rev. 07 — 25 February 2009
2
RECEIVER
C-bus is illustrated in
SLAVE
TRANSMITTER/
RECEIVER
Universal LCD driver for low multiplex rates
SLAVE
TRANSMITTER
MASTER
STOP condition
Figure
P
PCF8566
TRANSMITTER/
© NXP B.V. 2009. All rights reserved.
13.
RECEIVER
MASTER
mbc622
mga807
SDA
SCL
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