MC68HC711E9FU Freescale Semiconductor, MC68HC711E9FU Datasheet - Page 142
MC68HC711E9FU
Manufacturer Part Number
MC68HC711E9FU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711E9FU.pdf
(242 pages)
Specifications of MC68HC711E9FU
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
12KB
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Timing Systems
9.5.2 Timer Interrupt Flag Register 2
Bits of this register indicate the occurrence of timer system events. Coupled with the four high-order bits
of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven
system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0] — Unimplemented
9.5.3 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits control the pulse
accumulator and IC4/OC5 functions.
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
142
Set when TCNT changes from $FFFF to $0000
The RTIF status bit is automatically set to 1 at the end of every RTI period. To clear RTIF, write a byte
to TFLG2 with bit 6 set.
Refer to
Refer to
Always read 0
Refer to
Refer to
Refer to
9.7 Pulse
9.7 Pulse
Chapter 6 Parallel Input/Output (I/O)
9.7 Pulse
9.7 Pulse
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 9-23. Pulse Accumulator Control Register (PACTL)
Accumulator.
Accumulator.
Accumulator.
Accumulator.
DDRA7
$1025
$1026
Bit 7
TOF
Bit 7
Figure 9-22. Timer Interrupt Flag 2 Register (TFLG2)
0
0
= Unimplemented
PAEN
RTIF
6
0
6
0
M68HC11E Family Data Sheet, Rev. 5.1
PAMOD
PAOVF
5
0
5
0
PEDGE
Ports.
PAIF
4
0
4
0
DDRA3
3
0
3
0
I4/O5
2
0
2
0
RTR1
1
0
1
0
Freescale Semiconductor
RTR0
Bit 0
Bit 0
0
0
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