SL811HST Cypress Semiconductor Corp, SL811HST Datasheet - Page 8

• Manufacturer Part Number: SL811HST
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HST

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

3.1.3.1 Control Register 1 [Address = 05h]
The Control Register 1 enables/disables USB transfer operation with control bits defined as follows.
Table 3-11. Control Register 1 [Address 05h]
At power-up this register will be cleared to all zeros.
Low-power Modes [bit 6 Control Register, Address 05h]
When bit-6 (Suspend) is set to “1,” the power of the transmit
transceiver will be turned off, the internal RAM will be in the
suspend mode, and the internal clocks will be disabled.
Note: Any activity on the USB bus (i.e., K-State, etc.) will
resume normal operation. To resume normal operation from
the CPU side, a data Write cycle (i.e., A0 set HIGH for a data
Write cycle) should be done. This is a special case and not a
normal direct write where the address is first written and then
the data. To resume normal operation from the CPU side you
must do a data Write cycle only.
Low-speed/Full-speed Modes [bit 5 Control Register 1,
Address 05h]
The SL811HS is designed to communicate with either full- or
low-speed devices. At power-up bit 5 will be LOW, i.e., for full-
speed. There are two cases when communicating with a low-
speed device. When a low-speed device is connected directly
to the SL811HS, bit 5 of Register 05h should be set to “1” and
bit 6 of register 0Fh, Polarity Swap, needs to be set to “1” in
order to change the polarity of D+ and D–. When a low-speed
device is connected via a HUB to SL811HS, bit 5 of Register
05h should be set to “0” and bit 6 of register 0Fh should be set
to “0” in order to keep the polarity of D+ and D– for full speed.
In addition, make sure that bit 7 of USB-A/USB-B Host Control
Registers [00h, 08h] is set to “1” for preamble generation.
J-K Programming States [bits 4 and 3 of Control Register
1, Address 05h]
The J-K force state control and USB Engine Reset bits can be
used to generate USB reset condition. Forcing K-state can be
Document 38-08008 Rev. *B
Bit Position
Reserved
Bit 7
7
6
5
4
3
2
1
0
Bit Name
Reserved
Suspend
USB Speed
J-K state force
USB Engine Reset
Reserved
Reserved
SOF ena/dis
Suspend
Bit 6
USB Speed
Bit 5
Function
0
“1” enable, “0” = disable.
“0” set-up for full speed, “1” set-up LOW-SPEED.
See the table below.
USB Engine reset = “1.” Normal set “0”.
When a device is detected, the first thing that must be done is to send it a USB Reset to
force it into its default address of zero. The USB 2.0 specification states that for a root hub
a device must be reset for a minimum of 50mS.
Some existing firmware examples set bit 2 but it is not necessary.
“1” = enable auto Hardware SOF generation; “0” = disable.
In the SL811HS, bit 0 is used to enable HW SOF auto-generation (bit 0 was not used in
the SL11H). The generation of SOFs is still occurring when set to 0, but SOF tokens are
not output to USB. (See )
0
J-K state force
Bit 4
USB Engine
used for Peripheral device remote wake-up, Resume and
other modes. These two bits are set to zero on power-up.
Table 3-12. Control Register 1 Address 05h – Bits 3 and 4
USB Reset Sequence
A typical reset sequence consists of the following:
After a device is detected, write 08h to the Control Register
(05h) to initiate the USB reset, then wait the USB reset time
(root hub should be 50 ms), additionally some types of devices
like a Forced J-state, lastly set the Control Register (05h) back
to 0h. After the reset is complete, the auto-SOF generation
should be enabled.
SOF Packet Generation
The SL811HS automatically computes the frame number and
CRC5 by hardware. No CRC or SOF is required to be
generated by external firmware for the SL811HS although it
can be done by sending an SOF PID in the Host PID, Device
Endpoint register.
To enable SOF generation, assuming host mode is configured:
Notes:
1. Set up the SOF interval in registers 0x0F and 0x0E.
2. Enable the SOF hardware generation in this register by set-
3. Set the Arm bit in the USB-A Host Control Register.
2.
3.
Bit 4
Reset
0
0
1
1
ting bit 0 = 1.
Bit 3
Force K-State for low speed.
Force J-State for low speed.
Bit 3
0
1
0
1
Reserved
Function
Normal operating mode
Force USB Reset, D+ and D– are set LOW (SE0)
Force J-State, D+ set HIGH, D– set LOW
Force K-State, D– set HIGH, D+ set LOW
Bit 2
Reserved
Bit 1
SL811HS
SOF ena/dis
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Bit 0
[2]
[3]
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