M29W040B90N6T Micron Technology Inc, M29W040B90N6T Datasheet - Page 4

• Manufacturer Part Number: M29W040B90N6T
• Manufacturer: Micron Technology Inc

Specifications of M29W040B90N6T

• Lead Free Status / Rohs Status: Supplier Unconfirmed

M29W040B
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Table 4, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
and Output Enable and keeping Write Enable
High, V
value, see the Figure 8, Read Mode AC Wave-
forms, and Table 11, Read AC Characteristics, for
details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
Write operation. See Figures 9 and 10 Write AC
Waveforms, and Tables 12 and 13, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
Table 4. Bus Operations
Note: X = V
4/20
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Operation
IH
IH
IL
. The Data Inputs/Outputs will output the
.
or V
IH
.
IH
V
, during the whole Bus
V
V
V
V
E
X
IH
IL
IL
IL
IL
IL
, to Chip Enable
V
V
V
V
V
G
X
IH
IH
IL
IL
IL
V
V
V
V
V
W
X
IH
IH
IH
IH
IL
Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
be held within V
level see Table 10, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
til the operation completes.
Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 4, Bus Operations.
Block Protection and Blocks Unprotection. Each
block can be separately protected against acci-
dental Program or Erase. Protected blocks can be
unprotected to allow data to be changed. Block
Protection and Blocks Unprotection operations
must only be performed on programming equip-
ment. For further information refer to Application
Note AN1122, Applying Protection and Unprotec-
tion to M29 Series Flash.
Cell Address
Command Address
X
X
A0 = V
Others V
A0 = V
Others V
IL
IL
, A1 = V
, A1 = V
CC3
IL
IL
Address Inputs
or V
or V
, for Program or Erase operations un-
ID
IH
IH
CC
IL
IL
to be applied to some pins.
, A9 = V
, A9 = V
± 0.2V. For the Standby current
ID
ID
CC2
,
,
, Chip Enable should
Inputs/Outputs
Data Output
Data Input
Data
Hi-Z
Hi-Z
CC
E3h
20h
CC2
± 0.2V)
IH
. The
, the