AT49LV8192A-90TC Atmel, AT49LV8192A-90TC Datasheet - Page 3

• Manufacturer Part Number: AT49LV8192A-90TC
• Manufacturer: Atmel

Specifications of AT49LV8192A-90TC

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 3 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 25mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

AT49BV008A(T) Block Diagram
AT49BV8192A(T) Block Diagram
Device Operation
READ: The AT49BV008A(T)/8192A(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high-impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
ADDRESS
ADDRESS
INPUTS
INPUTS
RESET
RESET
VCC
GND
VCC
GND
VPP
VPP
WE
WE
OE
OE
CE
CE
Y DECODER
Y DECODER
X DECODER
X DECODER
CONTROL
CONTROL
LOGIC
LOGIC
DATA INPUTS/OUTPUTS
DATA INPUTS/OUTPUTS
PROGRAM DATA
PROGRAM DATA
INPUT/OUTPUT
INPUT/OUTPUT
MAIN MEMORY
MAIN MEMORY
(496K WORDS)
(992K BYTES)
PARAMETER
PARAMETER
PARAMETER
PARAMETER
BOOT BLOCK
BOOT BLOCK
I/O0 - I/O15
4K WORDS
4K WORDS
I/O0 - I/O7
BUFFERS
LATCHES
Y-GATING
8K BYTES
8K BYTES
16K BYTES
BUFFERS
LATCHES
Y-GATING
8K WORDS
BLOCK 2
BLOCK 1
BLOCK 2
BLOCK 1
AT49BV8192A
AT49BV008A
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
FFFFF
07FFF
05FFF
03FFF
00000
7FFFF
03FFF
02FFF
01FFF
00000
06000
03000
08000
04000
04000
02000
DATA INPUTS/OUTPUTS
DATA INPUTS/OUTPUTS
PROGRAM DATA
PROGRAM DATA
INPUT/OUTPUT
INPUT/OUTPUT
MAIN MEMORY
MAIN MEMORY
(496K WORDS)
BOOT BLOCK
BOOT BLOCK
PARAMETER
PARAMETER
I/O0 - I/O15
PARAMETER
PARAMETER
(992K BYTES)
I/O0 - I/O7
4K WORDS
4K WORDS
16K BYTES
8K WORDS
Y-GATING
8K BYTES
8K BYTES
Y-GATING
BUFFERS
LATCHES
BUFFERS
LATCHES
BLOCK 1
BLOCK 1
BLOCK 2
BLOCK 2
AT49BV8192AT
AT49BV008AT
7CFFF
FFFFF
FC000
FBFFF
F9FFF
F7FFF
7FFFF
7DFFF
7BFFF
FA000
00000
7E000
7D000
7C000
00000
F8000
3