AT49LV4096A-70TC Atmel, AT49LV4096A-70TC Datasheet - Page 2

• Manufacturer Part Number: AT49LV4096A-70TC
• Manufacturer: Atmel

Specifications of AT49LV4096A-70TC

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 3 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 25mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

2
AT49BV/LV4096A
AT49BV/LV4096A SOIC (SOP)
I/O10
I/O11
GND
VPP
I/O0
I/O8
I/O1
I/O9
I/O2
I/O3
A17
NC
CE
OE
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
The device is erased by executing the Erase command sequence; the device internally
controls the erase operation. The memory is divided into four blocks for erase opera-
tions. There are two 4K word parameter block sections, the boot block, and the main
memory array block. The typical number of program and erase cycles is in excess of
10,000 cycles.
The 8K word boot block section includes a reprogramming lock out feature to provide
data integrity. This feature is enabled by a command sequence. Once the boot block
programming lockout feature is enabled, the data in the boot block cannot be changed
when input levels of 5.5 volts or less are used. The boot sector is designed to contain
user secure code.
The BYTE pin controls whether the device data I/O pins operate in the byte or word
configuration. If the BYTE pin is set at a logic “1” or left open, the device is in word con-
figuration, I/O0 - I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O
pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function.
RESET
AT49BV/LV4096A TSOP Top View
VPP
A15
A14
A13
A12
A11
A10
A17
WE
NC
NC
NC
NC
NC
A9
A8
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Type 1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
1618H–FLASH–4/04