LH28F008BJT-TTLZ2 Sharp Electronics, LH28F008BJT-TTLZ2 Datasheet
LH28F008BJT-TTLZ2
Specifications of LH28F008BJT-TTLZ2
Related parts for LH28F008BJT-TTLZ2
LH28F008BJT-TTLZ2 Summary of contents
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... Flash Memory LH28F008BJT-TTLZ2 Date Dec. 13. 2001 ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 1.3 Product Description...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization................................................. 4 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 8 3.1 Read.............................................................................. ...
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... These alternatives give designers ultimate control of their code security needs. The product is manufactured on SHARP’s 0.25µm ETOX 40-lead TSOP, ideal for board constrained applications. *ETOX is a trademark of Intel Corporation. LH28F008BJT-TTLZ2 8M-BIT ( 1Mbit ×8 ) Enhanced Automated Suspend Options Byte Write Suspend to Read ...
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... INTRODUCTION This datasheet contains the product specifications. Section 1 provides a flash memory overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Features Key enhancements of the product are: Single low voltage operation Low power consumption Enhanced Suspend Capabilities ...
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The access time is 100ns (t ) over the operating AVQV temperature range (0°C to +70°C) and V range of 2.7V-3.6V. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not ...
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Output Buffer Y Input A -A Decoder 0 19 Buffer Address X Decoder Latch Address Counter Figure 1. Block Diagram ...
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... V total of 80 hours maximum. DEVICE POWER SUPPLY: Do not float any power pins. With V V SUPPLY the flash memory are inhibited. Device operations at invalid V CC Characteristics) produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins ...
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... After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location ...
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... Refer to Table 5 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes ...
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Top Boot [ FFFFF Reserved for Future Implementation FE003 Boot Block 0 Lock Configuration Code FE002 FE001 Reserved for Future Implementation FE000 Boot Block 0 FDFFF Reserved for Future Implementation FC003 FC002 Boot Block 1 Lock ...
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Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When the CUI additionally controls block CCW CCWH1/2 erase, full chip ...
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Bus Cycles Command Req’d. Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Full Chip Erase Byte Write Block Erase and Byte Write Suspend Block Erase and Byte Write Resume Set Block Lock-Bit Clear Block Lock-Bits ...
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Read Array Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another ...
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Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 8) ...
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... CC 4.12 Block Locking by the WP# This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. The lockable two boot blocks are locked when WP#=V ...
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Permanent Operation V RP# CCW Lock-Bit Block Erase V X CCWLK or >V V CCWLK IL Byte V IH Write Full Chip X V CCWLK Erase >V V CCWLK Set Block X V CCWLK Lock-Bit >V V ...
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WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above Range ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H Write Byte Data and Address Read Status Register No 0 Suspend SR.7= Byte Write Yes 1 Full Status Check if Desired Byte Write Complete FULL STATUS CHECK ...
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Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Byte Write Read Read or Byte Write ? Read Array Data Byte Write Loop No Done? Yes Write D0H Write FFH Read Array Data Block ...
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Start Write B0H Read Status Register 0 SR. Byte Write Completed SR.2= 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Byte Write Resumed Read Array Data Figure 9. Byte Write Suspend/Resume Flowchart ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V ...
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... PC board trace inductance. 5.3 V Trace on Printed Circuit Boards CCW Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V Power supply trace. The V CCW supplies the memory cell current for byte writing and block erasing ...
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... For the lockout voltage, refer to the specification. (See chapter 6.2.3.) 3) Data protection through RP# When the RP# is kept low during read mode, the flash memory will be reset mode, then write protecting all blocks. When the RP# is kept low during power up and ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Byte Write and Lock-Bit Configuration ................0°C to +70°C Storage Temperature During under Bias ............................... -10°C to +80°C During non Bias ................................ -65°C to +125°C ...
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AC Input/Output Test Conditions 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...
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DC Characteristics Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Auto Power-Save Current CCAS Reset Power-Down Current CCD Read Current CCR ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout during Normal CCWLK CCW Operations V V during ...
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AC Characteristics - Read-Only Operations Sym. t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV V ...
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AC Characteristics - Write Operations Sym. t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP#V Setup to WE# Going ...
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V IH ADDRESSES( CE#( ELWL V IH OE#( WE#( High Z DATA(D/ "1" SR.7(R) "0" WP#( RP#(P) ...
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Alternative CE#-Controlled Writes Sym. t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP#V Setup to CE# Going High SHEH ...
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V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ "1" SR.7(R) "0" WP#( RP#(P) V ...
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Reset Operations "1" SR.7(R) "0" RP#( "1" SR.7(R) "0" RP#( (B)Reset During Block Erase, Full Chip Erase, Byte Write or Lock-Bit Configuration 2. RP#(P) V ...
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Block Erase, Full Chip Erase, Byte Write and Lock-Bit Configuration Performance Sym. Parameter t Byte Write Time WHQV1 t EHQV1 Block Write Time t Block Erase Time WHQV2 t EHQV2 Full Chip Erase Time t WHQV3 Set Lock-Bit Time ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...