LH28F008BJT-TTLZ2 Sharp Electronics, LH28F008BJT-TTLZ2 Datasheet - Page 6

• Manufacturer Part Number: LH28F008BJT-TTLZ2
• Manufacturer: Sharp Electronics

Specifications of LH28F008BJT-TTLZ2

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

The access time is 100ns (t
temperature range (0°C to +70°C) and V
range of 2.7V-3.6V.
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical I
current is 2µA (CMOS) at 3.0V V
When CE# and RP# pins are at V
standby mode is enabled. When the RP# pin is at GND,
reset
consumption and provides write protection. A reset time
(t
are valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.
Please do not execute reprogramming "0" for the bit which
has already been programed "0". Overwrite operation may
generate unerasable bit. In case of reprogramming "0" to
the data which has been programed "1".
For example, changing data from "10111101" to
"10111100" requires "11111110" programming.
PHQV
·Program "0" for the bit in which you want to change
·Program "1" for the bit which has already been
data from "1" to "0".
programmed "0".
) is required from RP# switching high until outputs
mode
is
enabled
which
AVQV
CC
.
) over the operating
CC
minimizes
, the I
CC
supply voltage
CC
CMOS
power
PHEL
CCR
)
1.3 Product Description
1.3.1 Package Pinout
The product is available in 40-lead TSOP package (see
Figure 2).
1.3.2 Block Organization
This
architecture providing system memory integration. Each
erase block can be erased independently of the others up to
100,000 times. For the address locations of the blocks, see
the memory map in Figure 3.
Boot Blocks: The boot block is intended to replace a
dedicated
microcontroller-based system. This boot block 8K bytes
(8,192 bytes) features hardware controllable write-
protection to protect the crucial microprocessor boot code
from accidental modification. The protection of the boot
block is controlled using a combination of the V
WP# pins and block lock-bit.
Parameter Blocks: The boot block architecture includes
parameter blocks to facilitate storage of frequently update
small parameters that would normally require an
EEPROM. By using software techniques, the byte-rewrite
functionality of EEPROMs can be emulated. Each boot
block component contains six parameter blocks of 8K
bytes (8,192 bytes) each. The protection of the parameter
block is controlled using a combination of the V
and block lock-bit.
Main Blocks: The reminder is divided into main blocks for
data or code storage. Each 8M-bit device contains fifteen
64K bytes (65,536 bytes) blocks. The protection of the
main block is controlled using a combination of the
V
CCW
, RP# and block lock-bit.
product
boot
features
PROM
an
in
a
asymmetrically-blocked
microprocessor
CCW
CCW
Rev. 1.27
, RP#,
, RP#
or