LH28F008SAHT-T9 Sharp Electronics, LH28F008SAHT-T9 Datasheet - Page 14

• Manufacturer Part Number: LH28F008SAHT-T9
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAHT-T9

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Compliant

The Command User Interface itself does not occupy an ad-
dressable memory location. The interface register is a latch
used to store the command and address and data informa-
tion needed to execute the command. Erase Setup and
Erase Confirm commands require both appropriate com-
mand data and an address within the block to be erased.
The Byte Write Setup command requires both appropriate
command data and the address of the location to be written,
while the Byte Write command consists of the data to be
written and the address of the location to be written.
The Command User Interface is written by bringing WE# to
a logic-low level (V
are latched on the rising edge of WE#. Standard micropro-
cessor write timings are used.
Refer to AC Write Characteristics and the AC Waveforms
for Write Operations, Figure 9, for specific timing param-
eters.
5.
When V
the Status Register, intelligent identifiers, or array blocks
are enabled. Placing V
write and block erase operations as well.
SR. 7 = WRITE STATE MACHINE STATUS (WSMS)
SR. 6 = ERASE SUSPEND STATUS (ESS)
SR. 5 = ERASE STATUS (ES)
SR. 4 = BYTE WRITE STATUS (BWS)
SR. 3 = V
SR. 2-0 = RESERVED FOR FUTURE (R)
These bits are reserved for future use and should be masked
out when polling the Status Register.
COMMAND DEFINITIONS
1 = Ready
0 = Busy
1 = Erase Suspended
0 = Erase in Progress/Completed
1 = Error in Block Erasure
0 = Successful Block Erase
1 = Error in Byte Write
0 = Successful Byte Write
1 = V
0 = V
ENHANCEMENTS
PPL
PP
PP
PP
is applied to the V
STATUS (VPPS)
Low Detect; Operation Abort
OK
IL
) while CE# is low. Addresses and data
WSMS
PPH
7
on V
PP
PP
pin, read operations from
ESS
enables successful byte
6
Table 4. Status Register Definitions
ES
5
LHF08ST9
BWS
4
Device operations are selected by writing specific com-
mands into the Command User Interface. Table 3 defines
the LH28F008SAHT-T9 commands.
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode, the LH28F008SAHT-T9 defaults to
Read Array mode. This operation is also initiated by writing
FFH into the Command User Interface. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the Command User Interface
contents are altered. Once the internal Write State Machine
has started a block erase or byte write operation, the device
will not recognize the Read Array command, until the WSM
has completed its operation. The Read Array command is
functional when V
Intelligent Identifier Command
The LH28F008SAHT-T9 contains an intelligent identifier
operation, initiated by writing 90H into the Command User
Interface. Following the command write, a read cycle from
address 00000H retrieves the manufacturer code of 89H. A
read cycle from address 00001H returns the device code of
A2H. To terminate the operation, it is necessary to write
another valid command into the register. Like the Read Ar-
ray command, the intelligent identifier command is func-
tional when V
NOTES:
RY/BY# or the Write State Machine Status bit must first be
checked to determine byte write or block erase completion, be-
fore the Byte Write or Erase Status bit are checked for success.
If the Byte Write AND Erase Status bits are set to "1"s during a
block erase attempt, an improper command sequence was en-
tered. Attempt the operation again.
If V
before another byte write or block erase operation is attempted.
The V
continuous indication of V
V
quences have been entered and informs the system if V
not been switched on. The V
report accurate feedback between V
VPPS
PP
3
PP
level only after the byte write or block erase command se-
low status is detected, the Status Register must be cleared
PP
Status bit, unlike an A/D converter, does not provide
PP
R
2
=V
PP
PPL
=V
or V
PPL
R
1
PP
or V
PPH
PP
level. The WSM interrogates the
Status bit is not guaranteed to
.
PPH
PPL
R
0
.
and V
PPH
.
PP
has
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