LH28F016SCT-L90 Sharp Electronics, LH28F016SCT-L90 Datasheet - Page 10

• Manufacturer Part Number: LH28F016SCT-L90
• Manufacturer: Sharp Electronics

Specifications of LH28F016SCT-L90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

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2 PRINCIPLES OF OPERATION
The LH28F016SCT-L90 SmartVoltage Flash memory
includes an on-chip WSM to manage block erase,
byte write, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed power
supplies during block erasure, byte write, and lock-bit
configuration, and minimal processor overhead with
RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
byte writing, and lock-bit configuration. All functions
associated with altering memory contents−block
erase, byte write, Lock-bit configuration, status, and
identifier codes−are accessed via the CUI and
verified through the status register.
Commands
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
byte write, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification, and margining of data.
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, or outputs
status register data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and
executed from system RAM during flash memory
updates. After successful completion, reads are
again possible via the Read Array command. Block
erase suspend allows system software to suspend a
block erase to read or write data from any other
block. Byte write suspend allows system software to
suspend a byte write to read data from any other
flash memory array location.
PP
are
enables successful block erasure,
written
using
PP
voltage. High
standard
LHF16CZA
1DFFFF
1CFFFF
0DFFFF
0CFFFF
1FFFFF
1EFFFF
1BFFFF
1AFFFF
0FFFFF
0EFFFF
0BFFFF
0AFFFF
1D0000
1C0000
19FFFF
18FFFF
17FFFF
16FFFF
15FFFF
14FFFF
13FFFF
12FFFF
11FFFF
10FFFF
0D0000
0C0000
09FFFF
08FFFF
07FFFF
06FFFF
05FFFF
04FFFF
03FFFF
02FFFF
01FFFF
00FFFF
1F0000
1E0000
1B0000
1A0000
0F0000
0E0000
0B0000
0A0000
190000
180000
170000
160000
150000
140000
130000
120000
110000
100000
090000
080000
070000
060000
050000
040000
030000
020000
010000
000000
Figure 3. Memory Map
64K-byte Block
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64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
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64K-byte Block
31
30
29
28
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21
20
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18
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15
14
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11
10
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3
2
1
0
Rev. 1.2
7