TE28F004B5B80 Intel, TE28F004B5B80 Datasheet - Page 8
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TE28F004B5B80
Manufacturer Part Number
TE28F004B5B80
Description
Manufacturer
Intel
Datasheet
1.TE28F004B5B80.pdf
(44 pages)
Specifications of TE28F004B5B80
Cell Type
NOR
Density
4Mb
Access Time (max)
80ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
19b
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8b
Number Of Words
512K
Supply Current
70mA
Mounting
Surface Mount
Pin Count
40
Lead Free Status / Rohs Status
Not Compliant
28F200B5, 28F004/400B5, 28F800B5
2.2
Intel
upgrade paths in each package pinout up to the
8-Mbit density. The 44-lead PSOP pinout follows
the industry-standard ROM/EPROM pinout, as
shown in Figure 1. Designs with space concerns
should consider the 48-lead pinout shown in
Figure 2. Applications using an 8-bit bus can use
the 40-lead TSOP, which is available for the 4-Mbit
device only.
8
WP#
BYTE#
V
V
GND
NC
CC
PP
Symbol
®
5 Volt Boot Block Flash architecture provides
Pinouts
INPUT
INPUT
Type
WRITE PROTECT: Provides a method for unlocking the boot block with a logic
level signal in a system without a 12 V supply.
When WP# is at logic low, the boot block is locked, preventing program and
erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the status register to indicate the operation
failed.
When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.
NOTE: This feature is overridden and the boot block unlocked when RP# is at
V
not have enough pins, it does not include this pin and thus 12 V on RP# is
required to unlock the boot block. See Section 3.3 for details on write protection.
BYTE# ENABLE: Configures whether the device operates in byte-wide mode (x8)
or word-wide mode (x16). This pin must be set at power-up or return from deep
power-down and not changed during device operation. BYTE# pin must be
controlled at CMOS levels to meet the CMOS current specification in standby
mode.
When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ
address that decodes between the upper and lower byte. DQ
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is
read and programmed on DQ
Not applicable to 28F004B5.
DEVICE POWER SUPPLY: 5.0 V
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5 V
be applied to this pin. When V
against Program and Erase commands.
GROUND: For all internal circuitry.
NO CONNECT: Pin may be driven or left floating.
HH
. This pin can not be left floating. Because the 8-Mbit 44-PSOP package does
Table 2. Pin Descriptions (Continued)
0
0
PP
–DQ
–DQ
Name and Function
Pinouts for the corresponding 2-, 4-, and 8-Mbit
components are provided on the same diagram for
convenient reference. 2-Mbit pinouts are given on
the chip illustration in the center, with 4-Mbit and
8-Mbit pinouts going outward from the center.
< V
7
15
PPLK
and DQ
10%
.
all blocks are locked and protected
15
/A
–1
becomes the lowest order
PRELIMINARY
10% or 12 V
8
–DQ
14
are tri-stated
5% must