MT4LC8M8C2TG-5 Micron Technology Inc, MT4LC8M8C2TG-5 Datasheet
MT4LC8M8C2TG-5
Specifications of MT4LC8M8C2TG-5
Available stocks
Related parts for MT4LC8M8C2TG-5
MT4LC8M8C2TG-5 Summary of contents
Page 1
... C2 version and A12 on P4 version MEG x 8 EDO DRAM PART NUMBERS -5 PART NUMBER -6 MT4LC8M8C2DJ-x MT4LC8M8C2DJ-x S MT4LC8M8C2TG-x None MT4LC8M8C2TG MT4LC8M8P4DJ-x MT4LC8M8P4DJ-x S MT4LC8M8P4TG-x MT4LC8M8P4TG speed GENERAL DESCRIPTION The 8 Meg x 8 DRAM is a high-speed CMOS, dy- namic random-access memory devices containing 67,108,864 bits and designed to operate from ...
Page 2
... ADDRESS 11 BUFFER(11) REFRESH CONTROLLER A0- A11 REFRESH COUNTER 12 ROW- ADDRESS 12 BUFFERS (12) NO. 1 CLOCK RAS# GENERATOR 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 FUNCTIONAL BLOCK DIAGRAM MT4LC8M8P4 (13 row addresses) CONTROL LOGIC 10 8,192 8,192 FUNCTIONAL BLOCK DIAGRAM MT4LC8M8C2 (12 row addresses) CONTROL LOGIC 11 4,096 ...
Page 3
... CAS#. Both devices provide EDO- PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFY- WRITE) within a given row. The 8 Meg x 8 DRAM must be refreshed periodically in order to retain stored data. DRAM ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description ...
Page 4
... DRAM. The refresh requirements are met by refreshing all 8,192 rows (P4) or all 4,096 rows (C2) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms ...
Page 5
... Any output at V OUT OUT DQ is disabled and in High-Z state 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...
Page 6
... V - 0. REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with t RAS# RASS (MIN) and CAS# held LOW; WE 0.2V; A0-A11, OE# and may be left open Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 SYMBOL ≤ 0.2V [MIN]) ...
Page 7
... Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 = +3.3V ±0.3V) CC SYMBOL MIN t AA ...
Page 8
... WRITE command hold time (referenced to RAS#) WE# command setup time WE# to outputs in High-Z WRITE command pulse width WE# pulse widths to disable outputs WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 = +3.3V ±0.3V) CC SYMBOL MIN t ORD ...
Page 9
... CAC ( RAC [MIN] no longer applied). With or without the t and CAC must always be met 16. Either RCH or RRH must be satisfied for a READ cycle. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/ 17. = +3.3V achieves the open circuit condition and is not CC referenced 18. WCS, operating parameters. ...
Page 10
... CLZ 0 t CRP 5 t CSH NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 READ CYCLE RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH t ACH COLUMN t RCS RAC t CAC ...
Page 11
... CAH 8 t CAS 8 10,000 t CRP 5 t CSH 38 t CWL RAD 9 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 EARLY WRITE CYCLE RAS t CSH t RSH t RCD t CAS RAD t ASC t CAH t RAH COLUMN t CWL t RWL t WCR t WCS t WCH VALID DATA -6 MAX ...
Page 12
... CAS 8 10,000 t CLZ 0 t CRP 5 t CSH 38 t CWD 28 t CWL Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 READ WRITE CYCLE t RWC t RAS t CSH t RSH t RCD t CAS RAD t ASC t CAH t RAH COLUMN t RWD t RCS t CWD t AWD RAC t CAC t CLZ OPEN ...
Page 13
... CAS 8 10,000 t CLZ 0 t COH CPA 28 t CRP 5 t CSH Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 EDO-PAGE-MODE READ CYCLE t RASP RCD t CAS ACH t ACH t ASC t CAH t ASC COLUMN COLUMN t RCS RAC t CAC t CLZ VALID DATA OES -6 MAX UNITS SYMBOL ...
Page 14
... ASR 0 t CAH 8 t CAS 8 10,000 CRP 5 t CSH 38 t CWL Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 t RASP RCD t CAS ACH t ASC t CAH t ASC COLUMN COLUMN t CWL t WCH t WCS WCR VALID DATA VALID DATA -6 MAX UNITS SYMBOL t 15 ...
Page 15
... CPA 28 t CRP 5 t CSH 38 t CWD 28 t CWL NOTE for LATE WRITE cycles only. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 EDO-PAGE-MODE READ-WRITE CYCLE t RASP t CSH RCD t CAS ASC t CAH t ASC COLUMN COLUMN t RWD t RCS t CWL AWD t CWD CPA ...
Page 16
... CAH 8 t CAS 8 10,000 t COH CPA 28 t CRP 5 t CSH Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 (Pseudo READ-MODIFY-WRITE) t RASP t CSH CAS t CAS ASC t CAH t ASC t CAH COLUMN (A) COLUMN (B) t RCS CPA t RAC t CAC t CAC t COH VALID DATA ( SYMBOL ...
Page 17
... ASC 0 t ASR 0 t CAC 13 t CAH 8 t CAS 8 10,000 t CLZ CRP 5 t CSH 38 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 READ CYCLE (with WE#-controlled disable) t RCD RAD t RAH t ASC ROW COLUMN t RCS OPEN -6 MAX UNITS SYMBOL RAC ...
Page 18
... CRP 5 t CSR 5 t RAH 9 NOTE: 1. End of first CBR REFRESH cycle. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) t RAS t RAH ROW OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) t RAS ...
Page 19
... CLZ 0 t CRP NOTE HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 HIDDEN REFRESH CYCLE (WE# = HIGH; OE# = LOW) t RAS t RSH t RCD RAD t ASC t CAH COLUMN t AA ...
Page 20
... NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode Once RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 SELF REFRESH CYCLE (Addresses and OE# = DON’ ...
Page 21
... SEATING PLANE NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 32-PIN PLASTIC SOJ (400 mil) .829 (21.05) ...
Page 22
... Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 8 Meg x 8 EDO DRAM D20_2.p65 – Rev. 5/00 32-PIN PLASTIC TSOP (400 mil) SEE DETAIL A 0.95 11.76 ± ...