MT48LC8M16A2P-6A Micron Technology Inc, MT48LC8M16A2P-6A Datasheet - Page 21
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MT48LC8M16A2P-6A
Manufacturer Part Number
MT48LC8M16A2P-6A
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC8M16A2P-6A.pdf
(74 pages)
Specifications of MT48LC8M16A2P-6A
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
5.4ns
Maximum Clock Rate
167MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
165mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
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Part Number
Manufacturer
Quantity
Price
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Commands
Table 7:
COMMAND INHIBIT
NO OPERATION (NOP)
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ
burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO refresh or self refresh
(Enter self refresh mode)
LMR
Write enable/output enable
Write inhibit/output High-Z
Truth Table 1 – Commands and DQM Operation
CKE is HIGH for all commands shown except SELF REFRESH
Notes:
Table 7 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional truth tables appear following “Opera-
tions” on page 24; these tables provide current state/next state information.
1. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
2. A0–A9; A11 (x4); A0–A9 (x8); or A0–A8 (x16) provide column address; A10 HIGH enables the
3. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
4. This command is AUTO REFRESH if CKE is HIGH and SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
6. A0–A11 define the op-code written to the mode register.
7. Activates or deactivates the DQ during WRITEs (0-clock delay) and READs (2-clock delay).
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM, which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge fea-
ture; BA0, BA1 determine which bank is being read from or written to.
and BA0, BA1 are “Don’t Care.”
for CKE.
CS#
H
L
L
L
L
L
L
L
–
–
L
21
RAS#
H
H
H
H
X
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CAS#
H
H
H
H
X
L
L
L
L
–
–
WE#
H
H
H
H
X
L
L
L
L
–
–
128Mb: x4, x8, x16 SDRAM
DQM
L/H8
L/H8
H
X
X
X
X
X
X
X
L
©1999 Micron Technology, Inc. All rights reserved.
ADDR
Bank/
Bank/
Bank/
Code
code
row
Op-
col
col
X
X
X
X
–
–
High-Z
Active
Active
Commands
Valid
DQ
X
X
X
X
X
X
X
Notes
4, 5
1
2
2
3
6
7
7